Mechanisms for improving sub-90nm etch processing
07/01/2004
The challenges for etch processing at sub-90nm include tighter critical dimension uniformity, and higher selectivity to maintain smooth sidewalls and control silicon recess. Plasma etch suppliers are committed to finding alternative means for achieving higher selectivity and minimizing resist distortion and sidewall roughening. By exploiting chemistry mechanisms and process parameters, the goal is to develop recipes capable of preserving the photoresist throughout the entire etch process. Solutions for these problems are presented.
Equipment manufacturers are in the midst of the arduous task of process and hardware development and system fine-tuning and modification in anticipation of the sub-90nm node. The need to address reductions in linewidth when using 193nm photoresist (PR) presents additional processing challenges for etch, including line-edge roughness and reduced selectivity [1]. At the device level, better control is needed to meet requirements for diminishing CD bias uniformity. The challenge is being met — production-worthy solutions are being developed for both dielectric and silicon etch applications (Fig. 1).
 Figure 1. During nitride mask open, a) 193nm photoresist twisting and sidewall roughness are reduced with b) advanced silicon etch processes. |
In the sub-90nm realm, small deviations in thickness and depth become compounded, and cleanliness becomes critical. Likewise, resist integrity and equipment design become fundamental in establishing the CD uniformity — chamber-to-chamber (CTC), lot-to-lot (LTL), and wafer-to-wafer (WTW) — required for high-volume production. Below 90nm, the post-lithography/etch CD range across the wafer must be limited to <5nm, 3σ.
Unlike 248nm PR, 193nm PR is soft and easily damaged at the edges, transferring its jaggedness down to layers beneath. Known as line-edge roughness (LER), it appears along the sidewalls of gate structures and trenches of dual-damascene and STI structures. Similar resist-induced striations are also seen in via contacts. The transfer of coarseness to trenches and vias can interfere with the continuity of thin seed and barrier layers, creating adhesion problems for subsequent plating, which can ultimately degrade device characteristics. To prevent other forms of distortion in the resist, the fragile resist film often requires passivation to limit interaction with polymer by-products of the etch process.
Dielectric etch challenges
The majority of dielectric etch applications will be utilized in backend processes with >50% used for dual-damascene applications. Low-k films will continue to pose challenges as novel materials are developed for sub-90nm technologies.
Dual-damascene (DD) processing consists of a large number of complex mask steps — up to 11 metal layers — each requiring a trench and via etch. Two critical metrics of the etch process include flat etch front and uniform trench depth. As the use of an intermediate etch stop layer is gradually being eliminated, the etch process must be inherently uniform to deliver trench depth control. A flat trench etch front, free of micro-trenching, is essential to the integrity of the barrier and copper seed layers. Variations in trench depth across the wafer as low as 5% will affect the resistance of the copper wiring and device performance. Moreover, at smaller linewidths, trench depths get correspondingly shallower, so that a given variation becomes a larger percentage of the total and more likely to cause problems. However, our internal studies have shown that the desired etch depth control can be achieved. Trench etch with <2% center-to-edge etch nonuniformity was demonstrated on a 90nm DD structure, processed in situ on an Exelan dielectric etch system.
Once defined, trenches can become receptacles for particles, which can interrupt the continuity of the barrier layer for copper deposition, creating an "open." The ITRS is specifying fewer particles at smaller dimensions — coupled with the fact that the number of particles increases substantially with a decrease in particle size — adding to etch challenges. At 90nm, the minimum particle size specified in the ITRS at 0.045µm is below the detection level of current metrology equipment. Killer defects, particles that are 0.12µm dia., can be reliably measured. Detecting sizes ≤0.08µm is less certain.
The primary source of particles comes from the polymer by-products of reactions with the fluorocarbon source gases during the etch process. When these polymers accumulate on the chamber walls, they can redeposit on wafers during subsequent runs. Thus, an ideal design for particle control confines the plasma away from the chamber walls with chamber cleans performed on a per-run basis. Established technologies such as Lam's Dual Frequency Confined (DFC) plasma source and Waferless AutoClean (WAC) technique have been effective in maintaining a clean process environment and enabling post-etch particle performance for next-generation devices. Figure 2 illustrates the value of this combination in a production environment.
 Figure 2. A bare 300mm silicon wafer displays average particles added/wafer pass of <10 for particles ≥ 0.12µm after being etched in a 2300 Exelan dielectric etch system. |
Following etch, the number of particles with ≥0.12µm dia. added to a 300mm silicon wafer averaged <10/wafer pass. WAC chamber cleans were automatically performed after each run, delivering a mean-time-between-cleans (MTBC) in excess of 300 RF hours.
Over the past few years, dielectric etch has weathered an assortment of organic and inorganic low-k films, spun-on and deposited. Today, the industry appears to have settled on a select few — fluorinated silicate glasses (FSG) and organosilicate glasses (OSG) — though the final configurations are more complex. Some device manufacturers are tweaking low-k chemistries to gain a competitive advantage, creating a variety of etch sub-recipes. Each OSG film is slightly different. Others prefer hybrid stacks consisting of organic low-k , OSG, and FSG. Integration schemes also require altered etch processes to cover the various choices among hardmasks and photoresists.
To address this growth in processing options, etch systems must be capable of operating over a wide range of conditions, including low and high pressure and low and high power. Systems must provide the stability, flexibility, and process window to handle recipe changes without affecting the etch process. As a result, dual-frequency technologies — because of the process control they provide — are emerging as the leading design approach for meeting these requirements.
Enhanced selectivity in dielectric etch
Current 193nm photoresists lack the selectivity required for fabricating advanced devices. Without adequate selectivity, sacrificial layers at intermediate mask levels must be introduced, which increases process complexity and cost. Additionally, extra mask levels might increase the aspect ratio of an etched feature from 2:1 to 6:1 for some frontend mask open applications. In general, longer processing times and extra steps increase manufacturing costs and fab cycle time.
One way to eliminate the additional process steps is to improve resist management and increase selectivity during the etch process. In dielectric etch, various approaches for enhancing selectivity have been attempted. One approach increases the amount of polymerizing gases, an undesirable practice since excessive amounts of polymer can limit etch depth capability, produce premature etch stop, and cause resist lines to tip over. Large amounts of deposited polymer can also induce stress in the resist, creating line distortion or "wiggle."
An effective solution lies in managing the generation and use of passivating polymer in the etch process, which requires controlling the dissociation and polymer formation processes. The objective is to deliver the optimum amount of polymer to the wafer with minimal spread to the chamber walls. The efficacy of this straightforward method has been demonstrated on hardmask open and high aspect-ratio contact (HARC) applications.
 Figure 3. Dielectric etching of a HARC using 193nm resist successfully demonstrates a top CD = 160nm, space = 180nm, and an aspect ratio of ~15:1. |
To successfully etch dielectric materials at aspect ratios >10:1, the reactor design and plasma chemistry must be well-balanced to provide high-energy ions to etch to depths >1µm, with enough mask protection to maintain CDs. The etch challenges are considerable — aspect ratios of current production devices are ~15:1 (Fig. 3) and are approaching >20:1 with a requirement of CD variation <10nm.
In addition to preserving the resist during etch, manipulation of pattern dimension by "trimming" processes prior to the etch step is becoming more common. Care must be taken during trimming, however, to avoid any negative impact to the subsequent etch steps. Used appropriately, the etch process can correct some of the incoming nonuniformity from the lithography step. For example, CD bias was adjusted during a mask open to give a nominal value of 125nm. As indicated in Fig. 4a, the average wafer CD of 145nm from lithography was reduced by 20nm following etch to the nominal value of 125nm. At the same time, the range of variation in CD across the wafer was also reduced from 15nm pre-etch to 9nm post-etch. Vertical sidewalls free of roughness were successfully produced uniformly across the wafer, due in part to enhanced 193nm resist selectivity (Fig. 4b).
Conductor etch challenges
The need for higher selectivity is a general etch issue, though dielectric and silicon etch have distinct solutions, dictated by very different process regimes and chemistries. At the sub-90nm node, spacer etch challenges begin to approach those traditionally associated with gate and STI etch. One solution applicable to all can be found in enhanced selectivity.
Conductor etch is evolving to a predominantly frontend process, and therefore has a direct impact on device performance. As with dielectric etch, there are a variety of materials to process. Clearly, the challenges are considerable, requiring rigorous process development to achieve greater precision and accuracy.
The design rule for each new technology node has a corresponding effect on the thickness of gate oxides and oxide liners, as well as on the thickness of the spacer, which is positioned adjacent to the gate. The growing need to control ion implant profiles beneath the gate is placing greater constraints on spacer etch. Next-generation devices are displaying gate oxides dipping below 12Å, and spacer thicknesses approaching 100Å. To etch spacers with straight profiles and control "pull-down" at the top of the spacer requires oxide-to-silicon selectivity of >10:1. A further caveat is that thinner spacers, in a related manner, have tighter within-wafer uniformity specifications.
The emergence of high-k materials along with ultrathin gate oxides compound the challenges of gate etch. High-k films, such as hafnium and aluminum oxides, are harder and more chemically resistant than SiO2 and, during etch, may release by-products that can redeposit onto the gate sidewalls and contaminate the chamber. Ultrathin gate and high-k film integration requirements can exacerbate silicon recessing of the source/drain regions during gate etch, spacer etch, and high-k removal.
Silicon loss is of particular concern during gate formation, where a recessed substrate next to the gate region can create current crowding at the edge of the recessed region, thereby increasing series resistance. The resulting degradation in drive current is significant in devices below 90nm. High-k processing requires new etch chemistries and high selectivity. Though these materials are new relative to conventional gate oxide, improvements in oxide-to-silicon selectivity are being demonstrated with the development of novel chemistries and system hardware to add range and flexibility to the etch process [2].
Resist trimming
Advanced exposure tools together with 193nm resists are expected to consistently achieve target CDs at 90nm and below. An additional challenge associated with 193nm resists is LER, posing difficulty in patterning smooth features, especially for line masks. The resulting irregularities in the patterned resist are due to irregular polymer deposition on feature sidewalls during etch and the molecular structure of the PR.
To circumvent complex and expensive resolution enhancement techniques, resist trimming, a compensatory technique, was developed and introduced around the 130nm node. By trimming the resist to fine-tune CDs, variations in the 193nm film can be reduced, transfer of irregularities to layers below lessened, and the incidence of LER decreased (Fig. 5).
 Figure 5. 193nm resist trimming in excess of 60nm can be achieved, a) maintaining smooth sidewalls and b) creating vertical profiles. |
An ideal trim process provides independent control of vertical and lateral resist etch rates to produce smooth, vertical profiles with minimal loss in resist thickness while maintaining CDs [3].
Trench depth accuracy
Similar to DD, trench depth accuracy is essential in shallow trench isolation (STI). Depth uniformity ensures better planarity after chemical mechanical planarization (CMP). Since the oxide fill is conformal, larger divots over the deeper trenches result. STI is at the base of the device with subsequent levels layered on top of it. Any amount of topology will propagate upward. Depth uniformity is also important for controlling underlying implant profiles.
 Figure 6. The AFM shows the effectiveness of endpoint techniques, such as the Lam Spectral Reflectometer (LSR), in achieving trench depth accuracy to <10nm. |
The difficulty in depth uniformity is that STI is essentially a blind etch, relying on repeatable etch rates WTW. As linewidths become narrower, advanced monitoring techniques for endpoint control are required. With endpoint techniques such as spectral reflectometry, shallow-trench depth accuracies to <10nm can be achieved (Fig. 6).
Stepping up process control
As processing complexity and costs increase, so does the need for fault detection. Today, with more than twice the number of devices on a 300mm wafer, the ability to detect process problems as early as possible is crucial. Advanced process control provides a means of flagging trouble in equipment status as well as in the interaction between systems. For instance [4], when an etched wafer goes into a metrology tool for measurement, in the event the wrong recipe was run, a detected fault will halt the etching of subsequent wafers.
Integrated optical CD metrology (IM) will likely be required at the 65nm technology node to address tighter uniformity specifications in trench depth and CD bias. By feeding back metrology data to the previous step or forward to the next, adjustments can be made to process equipment parameters to compensate for nonuniformities. Optimizing gas distribution, chemistry, electrode temperature, and other parameters within the etch chamber can substantially improve CD uniformity. However, nonuniformities introduced at the previous lithography step can be offset with IM. The effectiveness of this technique has been demonstrated in internal studies at Lam to minimize WTW CD variation. Resist profile information was fed forward to the resist trimming step for fine-tuning, reducing variations WTW by an order of magnitude from 26nm to ~1nm.
Maintaining productivity
Performance milestones are only part of the equation for successful transition to a new technology node. The other is maintaining productivity — high throughput, high MBTC, and high MTBF. Current etch systems are reliable and production-worthy; however, as process complexity mounts, accompanying productivity cannot be assumed. It behooves etch equipment suppliers to maintain productivity by focusing on enhancing efficiency and reducing cost/function.
One way to reduce device manufacturing costs is with in situ processing: combining multiple process steps in one chamber. During trench formation, for example, an oxide trench etch, resist removal, and a nitride or carbide liner etch are performed in one chamber. Alternatively, a single reactor can perform a resist trim, ARC open, dielectric open, pad oxide etch, in situ strip, and shallow trench etch. The contribution to productivity is a reduction in capital expenditures, personnel, and cycle times [5].
Conclusion
The next-generation technology node will require continued development of new techniques and processes. Novel materials, such as porous low-k films, may offer the necessary k effective values <2.2, but present a new set of etch challenges. The porosity itself may create unusual nonuniformities when etched, making it difficult to create smooth walls on device structures. The pores can potentially act as reservoirs of etch gases and process by-products, interfering with subsequent processing steps. These fragile materials may also be more susceptible to damage from energetic ions during the etch process, and post-etch treatments, such as resist stripping, may lead to chemical modification of the material, potentially increasing the dielectric constant k above the as-deposited value.
The challenges for sub-90nm have been clearly delineated, from tighter CD uniformity and higher selectivity, to clean sidewalls and silicon recess control. Solutions to these problems have been demonstrated, and new challenges are already being addressed.
Acknowledgments
Exelan is a registered trademark of Lam Research Corp. Dual Frequency Confined, DFC, Lam Spectral Reflectometer, LSR, Waferless AutoClean, and WAC are trademarks of Lam Research Corp.
References
- S. Lassig, E. Hudson, "Integrating Dielectric Etching with 193nm Resists," Solid State Technology, Oct. 2002.
- T. Schram, et al., "Integrating High-k Dielectrics: Etched Polysilicon or Metal Gates," Solid State Technology, June 2003.
- S. Ramalingham, C. Lee, V. Vahedi, "Photoresist Trimming: Etch Solutions to CD Uniformity and Tuning," Semiconductor International, Sept. 2002.
- C. Petronis, R. Patrick, "Targeting Gate CD Using Feedforward APC and Voltage Control," Solid State Technology, Dec. 2003.
- R. Gottscho, J. LaCara, J. Tietz, "A Viable Solution: In Situ Processing for Etch," Solid State Technology, March 2003.
Bill Bosch received his BS in electrical engineering from Rochester Institute of Technology, and is product marketing manager for dielectric etch at Lam Research Corp., 4650 Cushing Parkway, M/S CA4, Fremont, CA 94538; ph 510/572-6321; fax 510/572-1560; e-mail [email protected].
Judy LaCara received her BS in chemistry from the U. of California, Berkeley, and is senior product marketing manager for conductor etch products at Lam Research Corp; e-mail [email protected].