Etch and CMP process control using in-line AFM
07/01/2004
As aspect ratios become higher, features become smaller, and requirements for planarity tighten, atomic force microscopy has begun to replace profilometry for topographic measurements such as trench and via depths, step height, and micro-planarity measurements, both in development and in production. The application of a high-throughput AFM for line monitoring in the STI and trench capacitor modules is described.
Previously confined to the research and development laboratory, atomic force microscopy (AFM) has become a necessary technology for monitoring trench depths and chemical-mechanical planarization (CMP) processes on the production floor, especially at the 90nm node and below. Smaller critical dimensions and tighter planarity requirements limit the ability of traditional profilers to monitor the shallow trench isolation (STI) process after CMP. Shrinking critical dimensions and increasing aspect ratios of trench capacitor structures have also made post-etch depth measurements inaccessible to traditional stylus profilers. Infineon Technologies now uses AFM to monitor its DRAM devices at STI and trench capacitor levels in production.
Process control by AFM has been limited in the past because of its relatively slow throughput and poor reliability. AFM operation has also required a high-level engineer, trained to separate AFM artifacts from real process issues. AFM line monitoring has often been capacity-limited for these reasons. Implementation of optimal sampling based on statistical models of the maturity of the process has not been feasible because the throughput of the AFM has been so limited. Placing multiple, redundant AFMs in the fab was not an option for reasons of cleanroom space and cost-of-ownership. To address these issues, a joint development program (JDP) between Infineon Technologies and KLA-Tencor was started. The goal was to develop a high-throughput AFM, capable of supporting development, ramp, and in-line process control for Infineon's STI and trench-capacitor processes at the 90nm node and beyond.
Surface metrology process control: STI CMP
The purpose of STI is to electrically isolate active device regions. Infineon/Siemens began replacing LOCOS isolation technology with STI at the 0.35µm node; beyond the 180nm node, many manufacturers made the change to STI. The use of STI enables an active area with higher device density.
 Figure 1. SEM cross-section of the STI region, after CMP and nitride strip. In this case, the isolated area (oxide) extends 17nm above the active area (silicon). |
After etch, STI features are typically filled with a high-density plasma oxide. CMP is used to planarize the device in preparation for subsequent process steps, and then the nitride hard mask is stripped. Fig. 1 shows the resulting structure.
Metrology issues post-CMP are illustrated in Fig. 2 and include:
- height difference between active area and dielectric, and
- erosion at interfaces between active area and dielectric.
By far the most critical metrology issue in STI CMP is the step height between the active and isolated regions after CMP and nitride strip. If this step exceeds a few nanometers, transistor parametric performance may be affected. If the oxide protrudes, it can interact with the polysilicon for the gate. Excessive active-isolated step height can also cause problems for implant and contacts. The step height can introduce difficulties for resist coverage and stepper focus, cutting into the depth-of-focus budget for the lithography step, which forms the gate.
The isolation trench (IT) step is influenced by trench depth, high-density plasma thickness, nitride thickness, CMP process parameters, and the process parameters for wet-chemical removal of residuals. Different tool combinations can generate lot-to-lot variation. Furthermore, wafers within a lot may be exposed to a variety of process chambers and CMP heads. Depending upon the matching conditions between these tools, a high number of wafers/lot and a high number of lots may need to be measured to ensure adequate process control. If the step height is out of specification and is not detected within the STI module, the consequences will not be seen until electrical test, when the transistor is finished, and many other similar wafers have been processed.
Erosion at the interfaces between active and isolated areas can affect the threshold voltage, Vt, and therefore have an impact on device performance. However, erosion is not monitored at this time — all of the AFM capacity reserved for the IT step is devoted to post-CMP step-height control.
The sub-nm noise floor of the AFM is important for monitoring IT step height, to identify step heights that exceed the stringent control limits. In addition to noise floor considerations, only an AFM with a sharp tip (terminal radius ≈10nm) can gather sufficient data points on the surface of each region to determine an accurate step height. Optical profilers are limited by their spot size and inability to distinguish which side of the step is higher. Furthermore, monitoring STI step height using any technique that relies on proxy structures is not recommended, because even small deviations of the shallow step height can lead to erroneous interpretation of the results. AFM alone constitutes the practical solution for this application.
At Infineon, AFMs have been successfully employed as CMP tool monitors, but the sampling plan has been limited by the throughput of the AFM. (Cleanroom space is limited, thus the number of tools is limited.) One of the main motivations for the JDP was the expectation that the 110nm and 90nm STI processes could be monitored more effectively by measuring a larger number of wafers. A higher-throughput AFM also enables the option of denser sampling for development of future nodes, and for in-line monitoring of those nodes with higher sampling frequency, as the devices enter production.
Trench capacitor etch recess
The requirement to have a large capacitor in a small space with low leakage is a main driver of DRAM technology. At the transition from 1Mb to 4Mb technology, planar capacitors failed to provide enough cell capacitance, and 3D capacitors replaced them throughout the industry. These took the form of either trench capacitors buried within etched holes in the silicon, or stacked capacitors built above the silicon in the region of the interconnect-level films.
For the trench capacitors considered here, a succession of polysilicon and insulator deposition and etch steps define the capacitor plates. A simplified version of Infineon's proprietary structure is given in Fig. 3. The first silicon etch step that defines the deep trench can be monitored using infrared metrology, as can the first polysilicon recess. The last two polysilicon recess depths, Ra and Rb in Fig. 3, are monitored during production by AFM because their control ultimately affects device performance.
Infineon had been using AFM for measuring the two key recess steps since the 0.25µm process was introduced. However, for the 70nm node and beyond, the AFM model currently used is not able to measure the structures adequately. Insufficient bottom travel has prevented the collection of enough data points to effectively represent the bottom of the trench, even though the AFM tips were clearly smaller than the structures. We believe that the solution lies in finding better scan algorithms. This performance gap represented another important driver of the joint development program.
Analysis of the process maturity suggests that trench-capacitor process control would benefit from a denser sampling plan (see next section). As with the STI module, the capacitor recess measurements have been limited by the AFM's throughput. Better process control of the trench-capacitor recess represents another JDP driver.
Other AFM measurements
AFM has unexploited capability for many high-resolution, local measurements in the fab. Having AFMs loaded to capacity for reasons of limited throughput has precluded most unscheduled small-lot or split-lot investigations of process issues that arise. On the other hand, having a high-throughput AFM that is not fully loaded would enable some of these issues to be addressed and decrease the number of expensive and time-consuming SEM measurements on cleaved wafers. The feedback time for the unit process engineers would be much shorter if an AFM could be used.
One example of an unexploited AFM application within the STI module is measuring the topography of the deposited oxide film before CMP. Monitoring the film topography post-CMP can help identify planarity issues and consequent leakage, if the deposited oxide is too thin. Another potential set of post-CMP AFM measurements within the STI module is to monitor microroughness or erosion at the interfaces. Such measurements will be of higher value at future technology nodes, when topographic requirements are tighter.
Another possible post-CMP AFM application is defect review, specifically for microscratches. Microscratches continue to be a problem for yield management post-CMP. Shallow scratches are nuisance defects, while deeper scratches can cause reliability problems after they are filled. With current optical and e-beam review methods, it can be difficult to distinguish shallow, nuisance scratches from killer defects. AFM may be able to differentiate nuisance from killer microscratches by measuring their size. However, a key barrier to using AFM for microscratch review is matching the coordinate system of the defect inspection system with that of the AFM.
These examples are confined to the STI module. Many other issues may arise during process development or production that could benefit from AFM measurements.
Sampling frequency and process control
When the sampling strategy within a module is not limited by the throughput of the measurement system, accepted statistical methods can be applied to determine the optimal sampling strategy for process control. Infineon has a release board that reviews process parameters and approves sampling strategies based on the method described below.
The process capability index Cpk is measured. This standard index is a function of the upper and lower control limits, as well as the standard deviation of the process parameter — for example, the trench depth. Cpk is a measure of how well the process is centered within the control limits, as well as how tightly the data are distributed around the center. When Cpk >1, the process is under control; moreover, a Cpk of 1.33 or better is usually considered a "good" process.
The variance components that contribute to Cpk can be broken down into three terms:
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The third term, representing systematic within-wafer variance, is not relevant to lot sampling; only random sources of error are of interest. Thus, we define SLS_rel as the variance relevant to lot sampling:
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The process capability index relevant to lot sampling, Cpk LS_rel is then defined as:
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Note that Cpk LS_rel ≥ Cpk. Examples showing high and low systematic within-wafer variance are given in Fig. 4.
Apart from process capability, as measured above, it is useful to define process stability. For this we use a desirability index, DI, which is an integrated assessment of process stability and control limit adjustment. The desirability index has three components: d1 gives the number of outliers; d2 represents the process variance change; and d3 captures the shift or trend in the process mean. They are defined as follows:
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The desirability index, then, is the geometric mean of their sum:
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However, we have found it useful to design a desirability index more sensitive to outliers:
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Note that when no outliers are present, istab = 0 and d1_5% = 1. When more than 5% of the data are outliers, d1_5% = 0. Then the modified desirability index can be written as:
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Bringing the process capability and desirability indices together, we define the process maturity, PM, as follows:
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Note that the second term is constructed to allow the desirability index to be weighted more heavily than the process capability index.
 Figure 5. The baseload factor (BLF) and its dependence upon process maturity (PM). (1: PM = 0 and BLF = 10; 2: PM = high and BLF = 1; 3: PM = 1.5 and BLF ~2) |
The baseload, BL, is the minimum number of lots/week sampled for a given process and product group. BL is determined by various fab-wide parameters. The baseload factor, BLF, is a multiplier for the baseload, and determines the sampling frequency, in lots/week, for a given metrology point. The baseload factor lies between 1 and 10 (see Fig. 5), and is given by:
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Thus, the sampling plan — the number of lots/week sampled — is a function of the process maturity.
Example values of Cpk, PM, and BLF are given in Fig. 6 for Ra, Rb, and the STI step measurements. These values are representative of the statistics of the three measurements during ramp of Infineon's 110nm process. Although production values are expected to be significantly better, the relationship among the values is expected to be preserved. The Cpk and PM values for the recess measurements will likely lie below that of the STI step measurement, and the BLF values for Ra and Rb should remain higher than that of the STI step measurement.
What these results indicate is that, for 100 lot starts/week, 100% of all lots should be sampled for the Rb measurement; 90% of all lots should be sampled for the Ra measurement; and 73% of all lots should be sampled for the STI CMP step measurement. With this level of sampling, Infineon would need to add AFM capacity. Considering that fab floor space is limited, the best solution is to replace current AFM tools with high-throughput systems.
Process control using AFM
Early results using the new AFM have not only enabled greater control of the STI and trench-capacitor processes by sampling the processes more frequently, but they have also demonstrated that the new tool provides better measurement capability for defining the depth of the trench capacitor recesses at the 70nm node than AFMs currently used in Infineon's fabs.
The target throughput improvement for the JDP is three times that of currently available AFM systems, under conditions that include wafer loading and unloading, alignment and pattern recognition on 200mm or 300mm wafers, and a 5-site measurement on each wafer. Under these conditions, the new AFM must also meet certain targets for repeatability, tip lifetime, and uptime. At the time of this writing, the system has achieved a >2× throughput increase, while meeting repeatability, uptime, and tip lifetime targets. It is anticipated that the JDP goals will be met in tandem with the general product release.
Using an AFM having a 2× throughput increase, Infineon's statistical modeling justifies increasing the sampling frequency of post-CMP STI and trench-capacitor etch process monitoring, without increasing the number of tools. This increased sample plan should result in tighter control of STI step heights and trench-capacitor etch depths during volume production. Potentially, better STI and trench-capacitor control may contribute, along with many other factors, to dispositioning a larger fraction of completed DRAM devices to the highest quality bins.
PFA efficiency
As an added benefit, higher throughput can create opportunity for additional engineering measurements. In many cases, cross-section SEM measurements or physical failure analysis (PFA), could be replaced by AFM scans. Removing a wafer from the lot for PFA incurs costs above that of diverting it for AFM analysis. Incremental PFA costs include the cost of the wafer lost from the lot plus incremental operator time, while incremental AFM cost is limited to the cost of the tip. The AFM result is available in a few minutes, whereas the cross-section results are not available until some hours later, in the best case. Furthermore, from the AFM data set, many different measurements can be derived by any engineer or operator using offline analysis software. In comparison, to get a new measurement using SEM cross-section, a specially trained PFA person must re-section the wafer. Even a slight modification to the cross-section to create a different view takes additional hours.
Using this simple model, it is estimated that PFA costs are 100–300× as much as AFM. Exact figures depend strongly upon detailed costs of each of these items, and these will vary by country and by fab. However, in any country and in any fab, the time to results will be at least a factor of 10 shorter for AFM than for SEM cross-section. During the hours necessary to obtain an acceptable SEM result, many lots of bad wafers may be processed, and have to be scrapped.
Conclusion
At Infineon, atomic force microscopy has become a necessary technology for monitoring trench depths and CMP processes at the 90nm node and below. Statistical models developed by Infineon show that its STI etch and trench-capacitor etch processes would benefit from more frequent sampling. A joint development program was started with KLA-Tencor to develop an AFM having throughput high enough to meet Infineon's needs for more frequent sampling without having to commit more floor space and operating budget to additional AFMs.
Using the new AFM, Infineon anticipates 1) better process control using the same number of tools; 2) the ability to respond more effectively to new process issues that may require small-lot or split-lot experiments; and 3) reduced operating costs when compared to physical failure analysis.
Thomas Trenkler is a process engineer within the metrology department at Infineon Technologies, PO Box 10 09 40, D-01079, Dresden, Germany; ph 49/351-886 7357; fax 49-351-886 7352, e-mail [email protected].
Rebecca Howland Pinto is principal scientist of the Surface Metrology Division at KLA-Tencor, 160 Rio Robles, San Jose, CA 95134; ph 408/875-1344, fax: 408/678-4531, e-mail [email protected].
This article has been modified from a version that was originally presented at the 29th Annual International Symposium on Microlithography and will be published in the SPIE technical proceedings.