San Jose — Packaging, assembly and test drive competitive solutions into the final manufacturing space
07/01/2004
J. Robert Lineback, Senior Technical Editor
Cheaper, faster, smaller, better—all of the good things being targeted by wafer fabs and Moore's Law of device shrinks are also squarely in the scope of final manufacturing and test technologies. Look no further than the show floor of Semicon West's final manufacturing segment in San Jose, where attendees can expect to get an eyeful of innovations in IC test, assembly, and packaging (TAP) technologies.
Along with faster final assembly tools and lower-cost materials for high pin-count wire-bonded ICs, Semicon West attendees will see the latest advances in wafer-level packaging (WLP) technologies, which are aimed at flip-chip and chip-scale packages (CSP). With WLP spreading, new tools and technologies are being applied to 300mm wafer-bumping processes, inspection tools, and materials, such as lead-free solder aimed at meeting global environmental guidelines.
Advanced packaging concepts will also be on display in San Jose. For example, Tessera Inc. is featuring its µZ Fold-Over package, which has been developed for multiple-chip applications containing processors, controllers, and memories stacked and housed with a footprint similar to a monolithic IC components. For both leadframe and array packaging applications, Dow Corning Corp. will be showcasing its DA-7000 and DA-8000 series of silicone die-attach materials that serve a range of applications, especially 3D stacked-die products and board-on-chip solutions.
In the wafer probe and final test arena, equipment suppliers are working hard to lower the cost of chip testing and to boost throughputs while dealing with the growing complexities of monolithic system-on-chip (SoC) devices and multichip system-in-package (SiP) products. To help ease the problem of test in mixed-signal SoCs and stacked-die SiP products, automatic test equipment (ATE) suppliers are adding features to leverage built-in self-test and design-for-test (DFT) functions now being embedded in ICs.
Test standards spread
Aiming to span requirements for DFT and structural test in analog, mixed-signal, and SoC products, Teradyne Inc. is displaying its FLEX semiconductor test system, which uses high-density instrumentation and the company's OpenFLEX architecture to enable reconfiguration of ATE platforms. Another two-year-old effort aimed at establishing open ATE industry standards plans to demonstrate progress in a number of test segments. Backed by Intel Corp., Motorola Inc., Advantest Corp., and others, the Open Semiconductor Test Architecture (OPENSTAR) will be demonstrated in a growing number of products offered by members of the Semiconductor Test Consortium (STC). For example, Advantest will show its OPENSTAR-based T2000 tester series for SoCs and other complex devices, serving computer, communications, and consumer electronics products.
Nextest Systems Corp. is featuring its Maverick Lightning platform, which adds full analog test capability to the Maverick ATE series. The new system can be configured with 128-pin analog testing capability. Speeding up DC/RF testing is also a key target of Keithley Instruments Inc.'s S680DC parametric test system, which uses a SimulTest parallel-test software to measure up to nine devices on wafers with a single probe touchdown. Another major trend to speed throughput has been a move to IC strip-testing. The approach tests ICs on strips of leadframes vs. individual components. Electroglas Inc. is showing its SIDEWINDER strip-test handling tool, which uses advanced 300mm prober technology.
Faster tools for tighter pad pitch
While the test segment pushes harder to lower costs, IC packaging and assembly suppliers are accelerating their efforts to quickly handle higher I/O ICs at lower costs as well. Kulicke & Soffa Industries Inc. will demonstate its new WaferPRO plus next-generation, single-pass stud bumper tool that bonds 22 bumps/second on wafer diameters up to 300mm. Other tools will also be demonstrated at Semicon West that address the ongoing trend toward tighter pad pitch and wire-bond connections in complex ICs.
High-speed dicing of wafers is a key feature of a water-jets guided laser system, called the LDS200A Laser-Microjet, from Synova SA. The system will dice chip sizes down to 0.25×0.25mm with a "cold laser" process. The Model 8000 gold ball-and-stitch thermosonic wire bonder from Palomar Technologies Inc. is capable of wire placement better than 5µm with high-speed throughput in complex multiple flip-chip product applications.
Applying technology from wafer fab applications, Suss MicroTec AG will show its new ABC200 automated bond cluster tool, which the company says takes up 40% less floor space than other manufacturing approaches for wafer-level processes. This tool is now aimed at MEMS encapsulation, silicon-on-insulator bonding, 3D packaging, and digital displays.
The need for innovation in inspection is growing for final manufacturing steps. Feinfocus' WBI-FOX system is a high-end x-ray inspection tool designed specifically for wafer-bump applications. An all-surface inspection system from August Technology Corp. is aimed at not only front and backside surfaces, but also wafer edges.
ATTENDEES' CHOICE AWARDS
How to Vote for Your Favorite Semicon West Products
This year, Solid State Technology will sponsor the 2nd Annual Attendees' Choice Awards for Semicon West. Attendees of either or both the San Francisco (wafer processing) and San Jose (final manufacturing) shows can vote for the best products exhibited at each show in three separate categories:
- Best solution to a problem
- Most innovative product
- Best cost-of-ownership product
Ballots are available at Solid State Technology's booth (#5953 in San Francisco, #11407 in San Jose). Only one vote per attendee is allowed. Completed ballots must be submitted at these booths prior to 5:00 pm on the second day of each show.
Winners in each category will be announced on the last day of each show.
All voters who identify themselves on their ballots will be eligible for a drawing that will determine the winner of a new smart phone. Eligible voters need not be present at the drawing to win; the winner will be contacted the week after Semicon West.