System-in-package update
06/01/2004
Nearly every product and component roadmap in the electronics industry is driven by miniaturization. The primary mechanism for increasing semiconductor density has been the decrease in transistor size made possible by improvements in process and design technology. The technical challenges and investment required to continue this path are significant, though, and system-in-package (SIP) technology has become an alternate integration approach.
During the lengthy industry debate about the relative merits of SIP vs. SoC (system-on-chip) technologies, a common conclusion has been that SoC is likely the best option for very high volume products that justify the up-front design costs and long development cycle time. Also, SoC can be a good option when the functions being integrated use similar silicon processes, thus avoiding the challenges and inefficiencies of heterogeneous wafer-level device processing (Fig. 1) [1].
 Figure 1. SIP and SoC integration approaches are suitable for different types of applications. (Source: Maxtek) |
SIP technology addresses opportunities that do not match the profile for a suitable SoC application. The "sweet spot" for SIP includes applications with multiple device technologies, multiple device suppliers, and a short lead-time requirement.
SIP via die stacking
Die stacking technology has progressed significantly in the last two years (Fig. 2). For several years, die stacking within a single package was primarily for SRAM and flash memory for cell phone applications [2]. With some die-thinning capability and high-yielding devices, this technology met roadmap requirements for portable products. Strictly speaking, though, stacked memory is not a "system" in a package because an aggregation of memory does not have system-level functionality.
In 2003 and 2004, though, several suppliers promoted stacked die with enough functionality to qualify as a true SIP. ChipPAC, the large subcontractor that announced a merger with STATS earlier this year, presented a six stacked-die CSP with a DSP or ASIC, plus flash and SDRAM chips. The package is 17×17mm, with a 1.6mm profile and a pincount over 400. The chips are thinned to 75µm. The main application is in cell phones; ChipPAC is predicting 100% of cell phones will include stacked die components in 2004.
Flynn Carson of ChipPAC also published an extensive study of board-level reliability of die stacked SIPs for integration of logic and memory in cell phones [3]. With up to five die stacked within a CSP, the board-level reliability was found acceptable. Three different CSP form factors were evaluated (low ball count at 0.8mm pitch, medium at 0.8mm pitch, and higher at 0.5mm pitch). The work noted that memory-only die-stacks perform better in board-level reliability because of the lower ball count, relaxed ball pitch, and favorable layout. With logic included, board level reliability is marginal for some configurations with 0.5mm pitch and a high ball count.
Samsung researchers published another extensive study on SIP technology for logic plus memory in cell phones. This paper included electrical, thermal, EMI, power, reliability, and design information [4]. The approach showed significant benefits compared to single-chip packaging, especially for electrical performance, power consumption, and EMI shielding capability. EMI shielding is not often cited as an advantage for multidie packaging, but the authors found that the substrate used for interconnecting chips within the package served as an effective EMI shield for attached devices.
SIP via stacked packages
Stacking packages, another approach for system-level integration with packaging technology, is typically the best approach when bare die are not available, whether because of limits on bare die testing, or because of die supply issues. (Many IC suppliers have concerns about revealing sensitive information if bare die and the associated design and test information is released.) Stacked packages can also be a better approach than stacked die when there are frequent revisions to the die design or size. When stacked bare die are modified, the whole system might need to be redesigned. When standard packages are being stacked, a change to one of the chips inside affects only the internal features of one package.
Sharp recently reported on reliability benefits of stacking packaged and tested devices, rather than bare die, to create a SIP structure [5]. Due to the cost of bare die testing and the yield implications of incomplete testing, package stacking can decrease cost and improve yield and reliability, even though more package processing is involved. Various design details were studied for optimizing thermal cycling and drop test performance; e.g., the authors demonstrated the reliability benefits of adding "dummy" balls to improve the units' mechanical stability when mounted on boards.
SIP via wafer stacking
The third general category of SIP technology involves wafers in the stacking process, with multiple wafers or singulated chips being stacked onto other wafers. This approach actually begins to blur the lines between SIP and SoC, since some wafer stacking approaches essentially create a new wafer that can be processed as a single wafer.
The Association of Super-Advanced Electronics Technologies in Japan has continued work on chip stacking with interconnections provided by copper electrodes passing through ultrathin die [6]. This is not yet a mature technology, but extensive process development is addressing challenges. Two key processes being studied are low-temperature connection of 20µm-pitch Cu electrodes, and encapsulation of the 10µm gap between the stacked chips in this scheme.
The Fraunhofer Institute for Reliability and Microintegration in Germany is pursuing a similar chip-to-wafer stacking approach for SIP integration schemes [7]. The "interchip via" technology is also in the process development phase, and the recent work addresses handling of very thin chips, backside processing, and soldering.
SIP: Not just an interim solution
SIP sometimes is viewed as an interim solution to fill gaps while an SoC approach is developed [8]. It is certainly true that SIP is a way to enter the marketplace quickly before an SoC can be created. However, the many recent advances in SIP technology should make it a permanent part of the system designer's toolbox. One large semiconductor manufacturer summarized it well [2]: "Some have claimed that 3D-SIP and other high-density packaging technologies are only a stop gap waiting for full realization of future SoCs. In reality, 3D-SIP packaging technology can improve functionality of applications by permitting each company to supply the best technology to the smallest possible package consistent with ease of system integration."
Another major chip company has identified applications where SIP provides a 75% cost reduction compared to SoC [9]. It is noteworthy that IC manufacturers are promoting SIP technology [10]. Often, a time-to-market requirement is the deciding factor in pursuing a SIP approach, and those requirements are not likely to go away. In fact, the International Technology Roadmap for Semiconductors (ITRS) identifies "responding to rapidly changing complex business requirements" as one of the "grand challenges" facing the semiconductor industry as a whole [11]. SIP is a key technology for facing that challenge.
Plenty of SIP challenges left
It is widely agreed that SIP is "taking off" [9], although there still are challenges that must be addressed. Many of these involve logistical and business issues that the industry is solving. One author [12] has identified five barriers that need addressing for SIP to have an even greater time-to-market advantage over SoC: 1) identifying the best scenario for ownership of a SIP product (OEM, EMS, or IDM); 2) CAD tools that can address 3D design requirements; 3) SIP standardization; 4) SIP test program development; and 5) high-density substrate capabilities.
A new JEDEC committee (JC-63) has been formed to address the need for cooperation in the SIP area by working on standards for multichip packaging. In general, this and other efforts promoting cooperation among the many types of participants in SIP are needed. As the SIP sector grows, all involved parties are likely to find ways to work with each other to make sure that they do not miss the large opportunity of SIP.
References
- J. Powell, "Understanding the Tradeoffs: SIP vs. SOC," SiPs or SoCs? The Multimillion Dollar Question, MEPTEC Technical Symposium, Feb. 2004.
- M. Kada, T. Kimura, "3D System-in-Package Trend and Future Evolution," Fabless Forum, Sept. 2003.
- F. Carson, et al., "Board Level Reliability of Various Stacked Die Chip Scale Package Configurations," Proc. IMAPS 2003, p. 894.
- H.-K. Kwon, et al., "SIP Solution for High-End Multimedia Cellular Phone," Proc. IMAPS 2003: 36th Internat'l Microelectronics Symposium, p. 223.
- T. Sugiyama, et al., "Board Level Reliability of 3D Systems in Package," Proc. 53rd Electronic Components & Technology Conf. 2003, p. 1106.
- K. Tanida, et al., "Ultra-high-density 3D Chip Stacking Technology," Proc. 53rd Electronic Components & Technology Conf. 2003, p. 1084.
- P. Ramm, et al., "3D System Integration Technologies," Mat. Res. Soc. Symp. Proc., Vol. 766, 2003.
- S. Bruederle, "Wireless SOC Demands Complex Process Tech.," Gartner Research Br., Oct. 22, 2002.
- G. Meyer-Berg, "SIP Developments: A Company Strategy and Perspective," 10th Annual Internat'l KGD Packaging and Test Workshop, Sept. 2003.
- .J. Tully, "Predicts 2004: Semiconductors," Gartner Dataquest, Dec. 17, 2003.
- International Technology Roadmap for Semiconductors, 2003 Edition.
- Y. Kim, "Solving SIP Time-to-Market Challenges," MEPTEC Review, Second Quarter 2004.
Jeffrey C. Demmin is on the advisory board of Solid State Technology; ph 408/383-3691, e-mail [email protected].