300mm: Friend or foe?
06/01/2004
Solid State Technology asked industry experts to weigh in on what the rise of 300mm manufacturing means to the industry.
300mm manufacturing: No drop in equipment demand
 James W. Bagley |
James W. Bagley, CEO, Lam Research Corp., Fremont, CA
As I look at the progression of the 300mm-wafer transition, I'm struck by how much has been said and written, how many widely diverging forecasts and predictions have been made, and how much general commentary there has been. Recently, an analyst suggested that because the new generation of 300mm tools is so capital-efficient, overall equipment demand will decline. Based on the lessons of nearly 40 years in the semiconductor industry, I believe this is a misconception.
First, the record shows us that the same concerns were raised during the two previous wafer-size transitions — from 75mm and 100mm to 150mm in the late 1970s and early 1980s, and then to 200mm in the late 1980s and early 1990s. In both cases, the capital efficiency of equipment improved, but a combination of economic growth and technological advances caused the basic capital-investment dynamic to stay approximately the same. The stage is set for a repeat of this at 300mm.
The first 200mm-capable equipment was introduced about 20 years ago as IBM led the conversion from 150mm to 200mm wafers. The industry was struggling with the 1985 downturn, and we were talking seriously about the "1µm barrier." Leading-edge technology was a sub-2µm MOS device with 12 mask levels. The metal interconnect was two levels of aluminum with a silicon dioxide dielectric. The basic production process and materials were stable; there was a sense that shifting to more efficient 200mm production would lower demand for equipment and jeopardize equipment industry growth.
However, the rapid adoption of the personal computer and the demand to improve its speed and memory capacity led to rapid industry growth and increased wafer fab investment. The drive of Japanese semiconductor companies to dominate the market — first in memory and then in logic — added a significant level of wafer fab investment. During this period, the technology evolution was spurred by the ITRS as individual semiconductor companies attempted to accelerate their technology ahead of the roadmap.
Technology acceleration caused a rapid reduction in feature size, added process steps and complexity, and added interconnect levels. Surging market demand and growing technical complexity meant that semiconductor manufacturers were implementing new technology while expanding capacity, which compounded the learning curve in their fabs. Thus, nearly a decade elapsed before 200mm sales surpassed 150mm sales. These combined events masked any decline in the equipment business due to the 200mm conversion.
Today, the industry believes that 300mm equipment, when fully mastered, will be more efficient than 200mm, both in terms of raw throughput and dollars/cm2 of silicon processed. But once again, economic conditions and technological advances are likely to limit the gains of capital efficiency.
From an economic perspective, we have been in an abysmal downturn, fueled by the collapse of the tech bubble in 2000 and by turmoil and uncertainty in the aftermath of the 9/11 attacks. Fortunately, we are finally seeing the excess capacity for trailing technologies fully utilized and demand for leading-edge devices starting to outstrip chipmakers' capacity to supply them.
In a strong-demand environment, manufacturers will invest aggressively to improve their market position at the leading edge. New entrants in the business, principally from China, will also invest aggressively in this up market. The wafer fab investment is now for a CMOS device with 27 mask levels and nine layers of copper interconnect utilizing a low-k dielectric. The attendant growth in process steps and the equipment necessary to perform the processes will demand significantly more capital investment per wafer processed. The wafer fab equipment investment for leading-edge devices will range from $50–$60 million/1000 wafer starts/month. The result is likely to be strong demand in the wafer-fab equipment segment as companies introduce new technologies with new materials and ramp capacity to capture market share.
On the technology side, semiconductor design and production are facing more uncertainty and change than at any time since the beginning of the industry 45 years ago. Metal interconnect has changed to copper with the incorporation of a wide variety of dielectric materials, most of which will be obsolete in one or two generations. Pushing critical dimensions below 100nm poses a myriad of challenges, from basic metrology to new gate structures and materials. Thin films will be specified in atomic layers with specifications approaching perfection. While equipment companies, our customers, and other research partners are doing outstanding work in bringing new technologies into production, we all face multiple learning curves, which will suppress productivity gains in the near future.
While the equipment industry faces many challenges, the 300mm transition is on course. The crossover point to 300mm will likely occur in 2004 or 2005 — nearly a decade after it began — just like the 200mm transition. The drop in equipment demand as some have forecasted is unlikely, and the long-term trend will be one of increasing capital intensity as technology evolution and semiconductor growth continues.
For more information, contact Jim Bagley, CEO, Lam Research Corp., 4650 Cushing Parkway, Fremont, CA 94538; e-mail [email protected].
Coexistence of 200/300mm: A new way to do business
 Aabid Husain |
Aabid Husain, director of marketing, DongbuAnam Semiconductor USA, Santa Clara, CA
The industry has adopted larger wafers approximately every 10–12 years; with each migration, the incumbent smaller wafer has all but disappeared. Given today's rapidly advancing technologies and increasing market diversification, there is evidence to question whether this pattern will hold for the 200 to 300mm migration.
Widespread adoption of larger wafer sizes takes place when two critical conditions are met: the manufacturing infrastructure is established, and the economics of transition to larger-diameter wafers make sense. While the infrastructure to manufacture 300mm wafers will be made available, the economics of moving from 200 to 300mm wafers are not so straightforward.
Many new applications will surely emerge over the next decade — with some becoming commoditized and following in the high-volume production footsteps of memory (DRAM, SRAM), similar to what was seen in the 1980s, and by "computation-centric" chips (microprocessor, DSP, etc.) in the 1990s. Consumer applications will continue to consume over 10 million units/year and benefit from processes at 90nm and beyond to be made available on 300mm wafers.
Ubiquitous applications over the next decade such as RFID, or sensor tags, will emerge, and these semiconductor devices will have to be produced in very high volumes and sold at extremely low prices, making 300mm manufacturing a seemingly perfect choice for implementation. Because some of these applications may not require the latest submicron process technologies, however, one wonders if mature processes (e.g., 0.25µm or 0.18µm) will ever be made available on 300mm wafers!
Conversely, Moore's Law — the predictable periodic increase in transistor density — is expected to prevail for the foreseeable future. As more and more functionality is squeezed into each square millimeter of silicon, there will be less and less silicon area required to implement a given set of functions, resulting in less silicon content for a given system. A good example is the DVD player. When the first ones came to market, they packed about a half dozen chips and sold for hundreds of dollars. Today, there are DVD players on the market that deliver the same or better performance with no more than two chips, and are priced at <$30. Thus, it cannot be taken for granted that all high-volume applications would migrate to 300mm wafers in the near future.
There will be many more new chips designed for applications that will be at moderate volume levels (1–2 million units/year) and will require deep-submicron technologies (90nm and 65nm). The PDA sector is a good example of a moderate volume market. With its requirement for low-power semiconductor devices, it makes perfect sense to use a 90nm process, but with a total market size of ~5 million PDAs/year and with three different silicon vendors supporting this market, the total volume requirement per silicon vendor comes out to be ~1 million semiconductor devices/year.
A similar case can be made for other sectors such as communications, where core router applications need the speed but are in moderate volume. Any thought of moving such devices to 300mm wafers should be quickly dismissed — the logistics and inventory management would not make sense. Since a typical wafer fab produces a 24-wafer batch, a single batch of 300mm wafers could easily yield a calendar quarter's worth of devices. No semiconductor manufacturer is likely to accept business consisting of running one 300mm wafer batch/customer every quarter. Since the infrastructure is well-established and the economies of scale are business-friendly, providing deep-submicron technologies on a 200mm wafer form factor seems logical for many such applications.
Successful semiconductor manufacturing companies will have to adopt a flexible business model that guides each customer to the optimal wafer size for its specific application(s). Some companies may offer multiple design runs from different customers on a 300mm wafer line as a way to justify the use of larger wafers. Such a strategy will require diligent foundry management to ensure that each customer's designs are confidentially processed along with production schedules, and inventory management will have to be tightly controlled. In considering the 200mm vs. 300mm question, it must be concluded that both wafer sizes should co-exist for the foreseeable future — a fundamental shift from the past.
For more information, contact Aabid Husain, director of marketing, DongbuAnam Semiconductor USA, 2953 Bunker Hill Lane Suite 206, Santa Clara, CA 95054; e-mail [email protected].