Advanced etch applications using tool-level data
06/01/2004
Semiconductor-manufacturing process control has historically relied on the dual approach of fixed statistical process-control (SPC) limits and limited metrology sampling. This approach, however, does not address sub-90nm requirements. Among the most challenging environments are lithography and etch, because of their direct impact on device performance. Applications of tool-level data in both AEC and APC approaches to reduce variance in etch performance are described.
With the accelerating drive toward smaller design rules, there is a corresponding increase in demand for chamber and process control. The urgency for advanced equipment control (AEC) and advanced process control (APC) has intensified at the 90nm design node, and both are anticipated to be essential for the 65nm node and below.
Given the requirements for complex multilevel processing, tool and wafer conditions need to be accurately monitored. The main goal is variance reduction, which allows improved high-end device performance yield. With AEC and APC, the challenge is to achieve run-to-run (R2R) process repeatability [1–3].
Optimizing performance with AEC
In terms of AEC, tool-level data can establish chamber baselines for tool and chamber matching, post-maintenance recovery, and process monitoring. A baseline fingerprint is a "health index," based on tool conditions and parameters. Typically, chamber-level data are available at a 1Hz rate, with a limited number of system variables (SVID). However, meeting sub-90nm process repeatability specifications necessitates a higher resolution of SVIDs. Deriving the full value from an increased data rate requires excellent data quality in terms of time stamping and absence of interrupts.
The most advanced etch platforms are capable of extracting up to 1000 SVIDs at a rate of 10Hz with low jitter (<5 msec). This fast rate provides the necessary resolution for capturing transient behavior that may contain essential information. Sub-90nm etch applications can have up to eight individual process steps with rapid changes between states. Repeatability of the transient periods between steps is necessary for consistent wafer performance. A simple example is shown in Fig. 1, which plots a comparison of gas pressure data taken at 1Hz and at 10Hz. The higher data rate allows for significantly improved resolution, and in this case an offset of 200 msec is detectable.
 Figure 1. 10Hz data collection enhances transient resolution over that achieved with 1Hz. |
The increased capture rate of the chamber SVIDs generates a massive volume of data that requires new methodologies to extract the most valuable information. A method of making this task manageable has been developed based on multivariate analysis (MVA). Traditional SPC methods are limited to individual parameters, while MVA can simultaneously process multiple parameters and weight them appropriately, reducing the result to a single score. Furthermore, with the score, it is possible to define dynamic excursion limits as a function of time.
The method is diagrammed in Figs. 2 and 3; it starts by establishing the score and a "golden trace." To obtain the score, it is necessary to first establish a collection recipe for the SVIDs as a function of time for a given sequence. A baseline is established by generating multiple runs. The next step is to collect and bundle the SVIDs into a single MVA score or figure of merit and combine all the runs into a golden trace. Figure 2 shows a typical plot of score vs. time for a multistep etch process. To capture any variances, it is necessary to collect a comparison sequence of runs and perform an overlay with the test runs against the baseline.
Given that all the SVIDs are captured where variances are detected, the analysis permits drill-down to identify the parameters that deviate the most from the baseline. The outcome of the final step allows the specific root cause to be identified for targeted corrective action. (The MVA in this paper was performed using Simca-P+ from Umetrics; for another example of MVA using neural nets, see [4].) The general sequence is shown in Fig. 3. In this representative case, MVA was used to analyze chamber drift for a production etch tool. Here, the initial baseline was the score as a function of time for a segment of the etch process (only the first step is shown). Approximately 50 SVIDs were captured and selectively weighted by the MVA to determine the score. After an extensive processing period, the chamber was fingerprinted again and the score trace established. The new score fingerprint was plotted in the second step, immediately revealing a deviation.
With drill-down analysis, the deviation was linked to a specific set of SVIDs associated with the plasma ignition step. The process drift issue could then be directly addressed and corrective action implemented. The chamber was fingerprinted again for the score, and this time the trace overlay showed nominal behavior. By using this type of monitoring, it is possible to establish optimal preventive maintenance cycles and minimize unscheduled downtime.
In the previous example, variations in chamber conditions were detected and eliminated through maintenance of the tool. In the next example, the variation in chamber and wafer results was corrected through process optimization. In this instance, process fingerprinting and optimization allowed across-lot consistency to be improved. Here, the MVA signature provided the information to characterize a subtle first-wafer effect associated with a periodic in situ dry-clean of the chamber (Fig. 4a).
Again, the chamber and dielectric all-in-one via etch process were baselined and the overall score was monitored for each wafer across many lots of data. The etch chamber clean was then modified away from the standard mode and a subsequent set of runs performed. The score for this set was observed to deviate from the baseline for each wafer immediately following the modified clean step. With drill-down, specific SVIDs showed a well-defined deviation from nominal that recovered on follow-on wafers.
The clean process was then corrected, and subsequent runs showed no deviation from the score for the baseline (Fig. 4b). In this case, only with the detailed tool-level data stream analysis was it possible to detect the differences, and consequently, to optimize the process sequence and obtain across-lot variance control. An important aspect of this case was that the score deviation correlated with important on-wafer features — CD performance and defectivity. In this manner, capturing a tool-level signature led to identifying conditions for improved wafer results.
Optimizing performance with APC
The goal of APC is to deliver process results that are consistently close to a target value. To deliver these results while tolerating incoming variation, it will be necessary to employ feedforward and feedback closed-loop control schemes [5]. Tool-level metrology (integrated or standalone) and process information can be used in these control schemes to improve on-wafer performance and achieve the desired tight distribution of output results. Here, the metrology facilitates R2R control. To date, closed-loop schemes have been created using a series of standalone systems in the process flow with some integrated configurations. Various etch systems can now be run with integrated optical metrology for multiple functions, including CD control, endpoint control, trench-depth control, and trench CD characterization. The most advanced etch systems also now incorporate tool-level feedforward and feedback.
If all tools used in a process operate within specifications and no systematic drift occurs in any output, the input and output of each tool can be expressed as an average value plus a finite "noise" value (variation). Feedforward etch control can reduce output noise below that of the input; i.e., variation in wafer-to-wafer post-etch CD can be reduced from the variation present in incoming patterning. Control effectiveness increases with the number of input characteristics for which the process can compensate (e.g., incoming pattern CD and sidewall angle, initial film thickness, etc.). A process response model determines etcher response that signals process adjustment(s) to the etcher.
Current applications employ input metrology information, such as CD or film thickness, to feedforward each wafer's condition and then adjust one or several of the etch process parameters to tune etch conditions (such as trim time, etchant gas flow, etc.). It is now possible to attain R2R control with the use of integrated metrology and multiparameter control. Multiple inputs and multiple outputs (MIMO) for feedforward into the control, as well as feedback, can help achieve exacting process control for advanced applications.
Gate etch, hard mask open, and other feature-sensitive applications can benefit from the flexibility to use multiple control variables to tune the process [6]. Gate CD control is a recognized requirement for advanced processes. In one case, APC with integrated metrology was used on polysilicon gate production wafers with photoresist mask to demonstrate enhanced R2R control and variance reduction. The incoming resist CD was measured with integrated metrology on a wafer-by-wafer basis, and this value was fed forward to modify the etch trim time as required; results are shown in Fig. 5.
 Figure 5. Process data showing a) variance reduction with CD feedforward for gate etch processing and b) wafer-by-wafer process control, reducing output variation. |
The pre-etch R2R CD distribution was measured as 13.9nm (3σ). Each wafer in all production lots was measured and the pre-etch CD was fed forward to the etch system controller. The controller computed the etch time for each wafer and processed it accordingly. The post-etch R2R CD distribution of 3.8nm shown in Fig. 5a is a 75% reduction from the pre-etch distribution. In addition, the mean CD is only 0.5nm from the target CD, demonstrating the system's tight control. Figure 5b shows that, in spite of significant incoming variation, wafer-to-wafer control can be achieved and output variance reduced even with only single-variable feedforward.
 Figure 6. Close agreement between integrated strip chamber post-etch and standard post-etch ex situ clean. |
It was also shown that other input parameters could be used in addition to the CD, with concomitant improvement in performance. Using multiple parameter inputs, it was possible to further reduce the post-etch distribution from 4.14nm (3σ) obtained using a one-parameter feedforward model to 1.61nm (3σ). Compared with the uncontrolled pre-etch distributions of >10nm (3σ), MIMO achieved close to an order-of-magnitude improvement. Moreover, given multiparameter input, the mean post-etch CD hit the target CD with only 0.1nm discrepancy.
The use of an integrated strip chamber to clean the etched structures after gate etch allows for accurate post-etch CD measurements, providing on-tool data feedback. Figure 6 shows that post-etch CD measurements taken with integrated metrology after an integrated strip agree exactly with measurements taken after the more standard approach of post-etch ex situ clean. This feedback allows the process to be adjusted for lot-to-lot variations. The significant aspect is that multiple inputs can be utilized for more sophisticated tuning that achieves dramatic improvement (Fig. 7). This solution eliminated send-ahead wafers and significantly decreased cycle time.
 Figure 8. Compared with a) open-loop control, integrated metrology with b) closed-loop control minimizes process variance for dual-damascene etch. |
For the case of dual-damascene, wafers were processed for the 90nm node at the Applied Materials Maydan Technology Center. The trench depth was ~4000Å. Automatic feedback control was implemented at the tool level using in situ optical metrology data. With the real-time optical depth measurements, it proved possible to improve Cp and Cpk values from 1.8 and 0.83 (open-loop) to 5.19 and 4.92(closed-loop), respectively (Fig. 8) — an improvement over timed etch. To characterize the processed damascene features, integrated OCD measurements have been shown to correlate well with SEM-CD and AFM-CD measurements.
Conclusion
Although AEC and APC have been discussed for more than a decade, the use of tool-level data has matured to be capable of delivering some of the anticipated benefits. As fab production moves toward 60nm and below, AEC and APC will become essential for wafer-by-wafer process control and tuning. It is now possible to monitor tools for R2R control and to substantially reduce output variance by both fingerprinting and MIMO control.
Chamber fingerprinting allows for improved copy-exact approaches, helps with process optimization, and improves overall equipment efficiency. With fingerprinting and monitoring, it is possible to reduce nonproduct wafer usage and unscheduled tool downtime. Integrated metrology is steadily becoming part of the production environment with tool-level feedforward and feedback for critical feature control. As evidenced by the cited cases of gate CD control and dual-damascene trench control, APC makes it feasible to achieve ITRS dimensionality control requirements for the 90nm node and below. These mechanisms for ensuring R2R repeatability will advance rapid process matching and speed new product qualification.
References
- M. Hankinson, T. Vincent, K. Irani, P. Khargonekar, "Integrated Real-Time and Run-to-Run Control of Etch Depth in Reactive Ion Etching," IEEE Transactions on Semiconductor Manufacturing, Vol. 10, No. 1, p. 121, 1997.
- C. Schneider, J. Smyth, A. Watts, "Automated Photolithography Critical Dimension Controls in a Complex, Mixed Technology, Manufacturing Fab," Proc. IEEE/Semi Advanced Semiconductor Manufacturing Conf., p. 33, 2001.
- A. Skumanich, "Improved Processing Performance with eDiagnostics and APC," Proc. Semi Technical Symposium, July 2003.
- S.J. Hong, G.S. May, J. Yamartino, A. Skumanich, "Automated Fault Detection and Classification of Etch Systems Using Modular Neural Networks," to be published in SPIE Conf. Proc. on Microlithography, from February 2004.
- B. Gasser, "The Future of Process Control Systems in High Performance Si Based Nanotechnology," AEC/APC Symposium, March 2003.
- D. Mui, et. al. "Advanced Gate Process Critical Dimension Control in Semiconductor Manufacturing," Proc. 12th Annual International Symposium on Semiconductor Manufacturing, 2003.
Andy Skumanich received his PhD in physics from the U. of California-Berkeley and is a senior technologist at Applied Materials, Santa Clara, CA 95054, ph 408/584-7610, e-mail [email protected].
John Yamartino received his PhD in physics from the Massachusetts Institute of Technology and is a technical staff member at Applied Materials.
David Mui received his PhD in electrical engineering from the U. of Illinois and is currently a senior technology manager of the Silicon Division at Applied Materials.
Dimitris Lymberopoulos is a technical staff member at Applied Materials.