Advanced techniques for 3D devices in wafer-bonding processes
06/01/2004
Wafer bonding is one of the most powerful processing techniques used in the fabrication and packaging of MEMS devices, which usually have three-dimensional architectures. Different approaches are currently in use: fusion, adhesive, eutectic, thermal-compression bonding (normally used for device fabrication and generation of 3D structures), and anodic bonding (the most used wafer-level packaging procedure). An overview of advanced techniques — in particular, the bonding of multiple wafers (triple stack bonding) and interface materials for high-vacuum compatible bonds — is presented.
The functions of wafer-level bonding for MEMS devices can be summarized into five main segments: first-level package, stress isolation, controlled ambient, higher level of integration, and new starting materials.
The main goal of assembly and packaging operations is to either attach the two halves of a device together (generally used in bulk micromachined sensors), or to provide a protective cover (common for surface-machined parts). Because it is performed prior to dicing, sealing a MEMS device at the wafer level provides a high level of cleanliness. Surface micromachined features are frequently first-level packaged at the wafer level to protect the sensitive, mechanically suspended features from the environment. Particle-sensitive MEMS features cannot be diced without being protected — cleaning of the chips after dicing is not very effective. In the case of surface-micromachined technology, bonding a cap wafer to a sensor wafer provides the required protection in preparation for the subsequent process steps.
Another advantage of wafer bonding is that a bonded wafer pair allows hermetically sealed mounting into the final package. Mechanical stress resulting from the interface between package and board has to be isolated from the silicon sensor chip; wafer-level bonding provides sufficient mechanical stability to decouple mechanical stress transferred from the sensor chip to the package. For example, pressure sensors use thick glass pedestals as a rigid mechanical base for the silicon sensor chip; the anodically bonded glass pedestal is generated at wafer level and absorbs any stress placed upon the final package.
A hermetic seal with controlled pressure inside the MEMS device is essential to adjust the mechanical characteristic of moving features. Dampening properties of an accelerometer or gyroscope are adjusted by encapsulating a defined gas ambient at precisely controlled pressure.
Wafer bonding also is seen as a way to increase the functional density of a device. Wafers with different functions, such as a mechanical sensor wafer and an ASIC wafer, can be combined at the wafer level, while 3D interconnect technologies allow electrical connections to be formed between devices at the wafer level.
Wafer bonding can also provide new starting materials for MEMS devices. Best-known examples are thick-film SOI wafers used for micromirror devices, and specially engineered substrates to produce pressure sensors.
 Figure 1. Bonding processes used in today's MEMS devices. (Data source: EV Group) |
The bonding process must be adapted to the needs and characteristics of devices. Many manufacturing sites are using matured high-yield bonding processes today. Although there are a large number of possible bonding processes published, very few reliable ones are used to produce the majority of manufactured devices (Fig. 1).
Bonding processes
Anodic bonding is considered the workhorse of MEMS packaging and accounts for the majority of all packaging applications. It is also quite common in MOEMS (optical MEMS) components because a transparent cover is needed, and is often used in fluidic-device assembly and pressure-sensor packaging. The popularity of anodic bonding for these applications is due to high bond yields, large process windows, and excellent alignment capability. Even though this process does not require intermediary substances to form a bond, the requirements for bond surface quality are less stringent than for fusion bonding approaches. Electric fields assist in the thermal diffusion of ions across the bond interface to achieve solid-state mixing of glass and silicon [3]. Advances in wafer clamping and independent thermal processes for top and bottom chucks are key to managing thermal-expansion differences and maintaining submicron alignment during whole-wafer processing.
Silicon direct bonding became widespread during the 1990s [1]. The technique is based on the principle that hydrophilic surfaces created by wet chemistry or plasma activation will immediately bond upon contact via van der Waals attractions between adsorbed water groups. Following the bond, batch thermal annealing is used to transition the bonds to covalent Si-O-Si bonds and achieve bond strengths equivalent to bulk silicon. Because silicon direct bonding requires atomic intimacy at the interface, point-of-use cleaning methods are essential in high-volume production. Numerous materials can be bonded using the technique, provided the surfaces meet the rigid roughness and flatness standards.
Modern cluster tools capable of cleaning, activation, aligning, and bonding can achieve throughputs of 25–40wph and are contained in Class 1 mini-environments. Silicon direct bonding is used in making SOI wafers for IC and MEMS fabrication, which are expected to replace 50% of the bulk silicon market and reach 1.8 million (200mm) wafers by 2005 [2].
Thermal-compression bonding includes three main subcategories: glass and glass fritt, eutectic, and diffusion. During glass fritt and glass bonding, the intermediate layer at the interface begins to flow under the influence of pressure when heated above the glass-softening temperature. The glasses can be applied via extrusion, screen-printing, spraying, or sedimentation methods.
Bonding techniques that use metals as intermediate layers typically form a hermetic seal and are compatible with high-vacuum processing environments (low-outgassing materials with low permeabilities). Eutectic bonding takes advantage of a metallurgical phase transformation in which the binary phase formed from constituents has a lower melting point than either solute.
In essence, eutectic bonding is a special case of a diffusion bond that allows very strong intermetallic bonds to be formed at relatively low temperatures. When two materials diffuse, a mixture is formed. This mixture has a very low melting point at the eutectic composition. Once the eutectic forms and becomes liquid, the reaction accelerates under the influence of liquid phase diffusion at the liquid-solid interface. Figure 2 shows a schematic of this process for the gold-silicon system. The reaction begins with interdiffusion and the eutectic is formed after resolidification from the melt.
Solid-state thermo-compression bonding is similar to eutectic bonding because an alloy is formed; however, these reactions do not involve melting of the diffused interface layer. In this type of bonding, the key is to identify systems with low-temperature solid-state phase transformations and rapid diffusion coefficients. Most often, this technique is used to enable conduction between the substrates. Metal layers deposited on one or both surfaces are used to form alloys with adjacent layers. The phase that forms is an intermetallic compound that is very tough and gives structural stability to the assembly. Formation occurs via diffusion and realignment of the atoms into stoichiometric structures.
Diffusion bonding is generally applicable to systems in which the diffusion coefficient is rapid at relatively low temperatures. This occurs for some face-centered-cubic metals such as gold and copper. It is therefore possible to create Au-Au and Cu-Cu bonds or even Cu-Au bonds at a low temperature using diffusion-driven kinetics. In these cases, no alloys are formed and the interface is a mixture of the two solutes, like sugar water. In some applications, a diffusion bond is preferable to intermetallic or eutectic alloy formation because of the generally brittle nature of those alloys.
New requirements and trends
Electrical integration of mechanical features at wafer level to the controlling CMOS-ASIC is one of the main research areas today. Many of today's existing bonding technologies use materials not compatible with CMOS or advanced packaging requirements: The presence of Pb (glass fritt bonding), Na (anodic bonding), or Au (thermal compression bonding) is a concern as soon as one of the wafers to be bonded is a CMOS wafer. Combining CMOS ASICs and MEMS through wafer-level bonding is becoming more attractive with progressive miniaturization. Throughput (bonding time of many die vs. bonding time of one wafer pair) and post-bond alignment accuracy (down to 1µm at 3σ) make wafer-level bonding the superior choice.
The increasing need to encapsulate in high-vacuum conditions is generated by oscillating MEMS features targeted for mobile consumer products. Power consumption at high sensitivity, as well as package size, are the major challenges. The high vacuum eliminates fluidic friction effects, thereby decreasing the device's power consumption (to maintain oscillation) and at the same time increasing its sensitivity to external input. The bonding process requires low-outgassing materials (which excludes polymers and glass fritts), hermetic seals, and a bonding temperature that allows the use of thermally fired getters to achieve very high vacuum (<1E-4mbar) subsequent to a vacuum bonding process (with <1E-2mbar in the device). New solders, diffusion bonding approaches, and eutectic alloys seem to be promising candidates for these requirements.
New intermediate layers such as polymers (epoxy, BCB, SU-8), eutectic alloys, and dry activated wafer bonding were developed to drive the required anneal temperature down from the 400–500°C range (in case of direct bonding even from >1000°C) to <200°C. Some of these technologies were originally developed for 3D interconnect applications, but have found additional applications throughout the MEMS technology sector.
Lower bonding temperature opens up the use of wafer-level bonding to CTE mismatched substrate combinations, biotech applications, and other materials with a temperature limit. A special case is dry activated bonding, originally developed to create SOI, and now being applied to MEMS packaging. The typical temperature required to achieve a bond strength >1J/m2 with an SiO2 interface is 500°C. With a mild plasma treatment of the wafer surface prior to bonding, this bond strength can be achieved at 200°C. An alternate approach uses spin-on glass at the interface, which lowers bonding temperature to a similar range while adding the ability to compensate for some topography. In addition, these processes provide hermetic seals and are compatible with high-vacuum processes. The requirements of surface roughness in the low nanometer range, as well as low total thickness variation and warp, have to be met in order to generate high-yield bonds. Off-the-shelf systems for R&D and volume manufacturing are now being introduced to the market.
 Figure 3. Configurations for anodic multistack bonding. |
Bonding more than two wafers at a time is used in several approaches including anodic, silicon direct, or any thermo-compression bond with an intermediate layer. In some cases, it was implemented out of necessity (to keep stress in a bonded triple stack low and symmetric). In other cases, multiple wafers are bonded for primarily economic reasons (i.e., increased throughput). Figure 3 shows all implemented scenarios for multiwafer anodic bonding.
Conclusion
Many MEMS factories have benefited greatly from choosing the right bonding method at the R&D stage. The device requirements must be clearly outlined before considering a wafer-level bonding approach. Many successful high-volume methods with attractive yield numbers and proven performance records have well-explored and understood limitations. Some emerging bonding technologies should be further developed with the specific MEMS device or application in mind. The driving force to transition to alternative bonding methods will be new requirements such as lower temperature, high vacuum, and CMOS compatibility.
References
- U. Goesele, Q.-Y. Tong, Semiconductor Wafer Bonding: Science and Technology, John Wiley and Sons, 1999.
- Silicon Wafer Bonding Technology for VLSI and MEMS applications, S.S. Iyer, A.J. Auberton-Hervé, eds., INSPEC, London, England, pp. xxi–xxii, 2002.
- M.J. Madou, Fundamentals of Micro-Fabrication, CRC Press, pp. 378–393, 1997.
Paul Lindner is CTO at EV Group, DI Erich Thallner Strafle 1, A-4780 Schärding, Austria; ph 43/7712-5311-0, fax 43/7712-5311-4600, e-mail [email protected].