Issue



USJ formation: Annealing beyond 90nm


05/01/2004







The formation of ultrashallow junctions (USJ) poses major challenges as device technology approaches the 65nm node. Three approaches for the formation of advanced USJ structures are described and the sheet resistance (RS) and junction depth (XJ) performance of the various techniques are compared.

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Three processes have potential to take the industry beyond the 90nm node: an extension of conventional spike-anneal, millisecond annealing, and solid-phase epitaxial growth (SPEG). Extending conventional spike-anneal technology — with reductions in the spike-anneal peak width — has the advantage of using conventional equipment and process integration schemes, combined with excellent uniformity and repeatability that meets the needs of volume production.

Millisecond annealing takes the spike-anneal concept to its ultimate limit by pulsed surface heating with millisecond peak widths at process temperatures just below the melting point of silicon. This technology has a major problem: the extreme temperature nonuniformity that can result from variations in optical absorption across the surface of the wafer. Other issues relate to the compatibility of advanced materials and device structures with extreme temperatures, thermal gradients, and induced stresses.

The third approach is SPEG, in which high dopant activation is achieved during low-temperature epitaxial regrowth of amorphous layers created by ion implantation. The challenges for this process mainly relate to process integration, dopant deactivation, and residual defects.

Despite the advantages of millisecond annealing and SPEG in the XJ/RS trade-off, the 65nm node is likely to require the combination of advanced ion-implant schemes and conventional spike anneals with minimized peak widths.

USJ formation and the scaling trend

The processes for forming USJ in source/drain extension regions of MOS transistors become increasingly important as device dimensions are scaled down. The degree of electrical activation of ion-implanted dopants has an impact on the parasitic resistance, and thus on the current drive capability, while control of the doping profile is critical for management of short-channel effects [1]. These requirements are reflected in the 2003 International Technology Roadmap for Semiconductors (ITRS) through the progressive minimization of the junction depth and the sheet resistance of USJ structures [2].

Shallow junctions are formed by low-energy ion implantation combined with rapid thermal processing (RTP) that provides a high-temperature anneal. As devices scale down, the trend has been to keep the junctions as shallow as possible by lowering implant energies and minimizing diffusion during RTP through the spike-anneal approach, where the wafer is ramped to a high temperature and then immediately allowed to cool. Spike annealing allows the use of high temperatures for effective dopant activation and damage annealing while restricting dopant diffusion by minimizing the effective anneal time [3].

As device technology approaches the 65nm era, the challenges for conventional RTP methods become especially evident for p-type doping because of the fast diffusion of boron combined with its relatively low solid-solubility limit, as compared to arsenic. This has stimulated exploration of many innovations in USJ technology, ranging from further refinement of conventional approaches to exotic methods such as pulsed-laser annealing [4]. For acceptance in volume manufacturing, these approaches must not only meet the XJ/RS target, but also be compatible with standard CMOS processing requirements and provide uniform and repeatable device characteristics.

Scaling the spike anneal

The most desirable path for the 65nm node is through further scaling of the spike-anneal approach. This requires no changes in the process integration scheme and benefits from the strong infrastructure of existing ion-implantation and RTP technologies. Further progress in the XJ/RS characteristics depends on innovations in the materials science, for example, through co-implantation of species that retard diffusion or increase activation, and through advances in RTP [4, 5]. For boron-doping, there is a benefit in increasing the peak temperature of the spike anneal while decreasing the anneal duration that arises from the difference between the thermal activation energy for diffusion and for electrical activation [6].

The challenge for conventional RTP is to reduce the dwell time at peak temperatures during the spike anneal, especially since this tends to be limited by the cooling rate of the wafer. Furthermore, the process uniformity requirements call for extraordinary control of temperature repeatability and uniformity across large-diameter wafers being ramped at rates of up to ~250°C/sec to temperatures of ~1050°C. An especially challenging aspect arises from the effect of variations in optical properties of wafers on heat transfer and temperature control in RTP systems, particularly temperature nonuniformity induced by the patterns that define device structures [7]. This pattern effect usually imposes the ultimate limit on temperature uniformity that can be achieved in RTP, although its magnitude is affected by the choice of heating configuration.


Figure 1. a) SIMS profiles display the impact of spike-anneal peak width on diffusion for two 300mm wafers implanted with 1015 BF2+/cm2 at 1.1keV and spike annealed at 1050??C (in Mattson RTP systems). b) Temperature-time profiles are shown.
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Figure 1 compares doping profiles for 300mm wafers implanted with 1015 BF2+/cm2 at an energy of 1.1keV and spike annealed at 1050°C using two different approaches for minimizing the peak width of the spike anneal. The temperature-time profiles are illustrated in Fig. 1b. The peak width of the spike profile at 50°C below the maximum temperature was 1.38 sec for the first approach, whereas it was 0.96 sec for the second approach. The reduction in thermal budget leads to a clear decrease in the dopant diffusion during the anneal. The lower thermal-budget process leads to ~7nm less diffusion, measured at a concentration of 5×1018/cm3, while the sheet resistance increased from 479Ω/sq. to 582Ω/sq. This translates into ~1.5nm of junction-depth reduction if the peak temperature is adjusted to obtain the same target sheet resistance.


Figure 2. The sheet resistance repeatability and uniformity on 300mm wafers during marathon testing of a 1050°C spike-anneal process.
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An essential requirement for the spike-anneal approach is repeatable temperature measurement and control so that each wafer experiences an identical temperature-time cycle, combined with excellent within-wafer temperature uniformity. Figure 2 shows on-wafer results from Mattson Technology's 3000 Plus RTP system, where the temperature uniformity and repeatability were evaluated using 300mm wafers implanted with 5×1015 B/cm2 at 10keV and annealed by spike anneals at 1050°C, where the sensitivity of RS to temperature was 0.76Ω/(sq. °C). The 1σ repeatability of RS was 0.16%, equivalent to ~0.2°C in temperature. The total range in mean RS was 0.45Ω/sq., which is equivalent to a temperature range of ±0.3°C. Uniformity measurements were performed at 121 points using a 5mm edge-exclusion region. The average 1σ uniformity was 0.82%, which is equivalent to ~0.9°C.

The XJ/RS values from narrow peak-width spike annealing at various peak temperatures are included in the XJ/RS comparison in Fig. 3, which contrasts results from various advanced approaches for USJ formation. To be consistent with the 65nm node requirements, the XJ values are taken at a background doping of 5×1018/cm3. The figure also includes the XJ/RS specified in the 2003 ITRS.


Figure 3. The relationship between sheet resistance (RS) and junction depth (XJ) for various USJ formation technologies; target values from the 2003 ITRS are included for comparison.
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The data comparison reveals a paradox because the spike-anneal results lie outside the ITRS box even at the 90nm node, but spike annealing is the only technique available for 90nm manufacturing. The discrepancy reflects the fact that design of real devices is far more complex than definition of a simple XJ/RS metric. For example, it has been shown that 65nm-node devices can be optimized by reducing the peak temperature of the spike anneal to limit dopant diffusion, while tolerating higher RS values [8]. The benefits of reduced implant energies and co-implantation schemes have also been demonstrated for 65nm-node device technologies [5]. The trend line through the spike-anneal points on Fig. 3 is extrapolated toward shallower junctions — the "gap" between the spike-anneal capabilities and the ITRS specifications at 65nm, and even those at 45nm, may indeed be manageable. Progressive reductions in spike-anneal peak width will be important because they allow the highest possible activation levels with minimum thermal budget.

Millisecond annealing

It has long been recognized that the quest for the optimal trade-off between defect annealing and dopant diffusion leads to the extreme of applying millisecond-duration anneals at temperatures just below the melting point of silicon [9]. Millisecond anneals typically require heating the wafer's surface with high-energy pulses of radiation that produce a large vertical temperature gradient that drives fast surface cooling. The heating power densities are ~1000× greater than in conventional spike annealing, and require the use of high-energy flash lamps or CW laser beams scanned across the wafer surface.

Figure 3 includes typical XJ/RS results from millisecond annealing, showing that the technique meets the ITRS requirements for the 65nm node [10]. The approach seems attractive because it may not require major changes in the process integration scheme. While the concept of millisecond annealing has been recognized for a very long time, there are many fundamental scientific and technological challenges that require solutions before the approach can become viable as a manufacturing solution. One severe problem arises from the pattern effect. This problem is already evident in conventional RTP, but the heating-power densities in millisecond anneals can produce far larger temperature gradients over much shorter-length scales.

Figure 4 shows theoretical predictions of the temperature nonuniformity expected during a pulsed annealing process that produces a peak temperature rise of 500°C in a plain silicon wafer. The figure illustrates the effects of two types of patterns: an isolated absorbing line that is 10µm wide and an array of 20 such lines, separated by 10µm spaces. Even the isolated line produces a temperature deviation of ~12°C, and in the array a much larger effect can be seen as a result of its larger spatial extent [11]. Although the process window for successful millisecond annealing has yet to be defined, it seems unlikely that such large temperature variations would be acceptable in manufacturing.


Figure 4. Predictions of the pattern effect in pulsed heating. The absorbing region heats to a higher temperature than the neighboring silicon, producing a large pattern-induced nonuniformity.
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Other challenges for millisecond annealing include the effects of large thermal stresses induced by vertical and lateral temperature gradients, as well as the question of the effect of high peak process temperatures and stresses on the new materials and device structures that are needed to stretch CMOS beyond 45nm.

SPEG

The third possible route for USJ technology beyond 65nm relies on exploiting the low-temperature epitaxial regrowth of ion-implantation amorphized silicon layers to provide highly activated junctions with minimal diffusion. The SPEG process, characterized extensively, can produce very high concentrations of electrically active dopants in silicon, even at relatively low temperatures of ~500°C [12].

Although SPEG has been an inherent part of implant annealing for many years, it has traditionally been followed by a high-temperature anneal, which removes damage that would otherwise remain after SPEG. The residual damage mainly lies slightly beyond the location of the original amorphous-to-crystalline silicon interface and is called end-of-range (EOR) damage. Residual defects within the depletion region of a p-n junction can increase leakage current. As devices scale down, the permitted junction leakage increases, and it has been suggested that an annealing process using only SPEG could produce very shallow, highly activated regions [13]. This may be attractive because it only requires conventional implantation and annealing equipment. The relatively low temperatures may also ease the introduction of new materials, especially high-k dielectrics and metal gates that may not be compatible with high-temperature annealing.

Figure 5a shows an example of a doping profile for a wafer that was processed using the SPEG approach. The wafer had been preamorphized by 1015 Ge/cm2 at 30keV and then implanted with 1015 B/cm2 at 500eV. The RTP anneal was performed in a gas ambient of 100ppm O2 in N2. The SPEG process leads to a shallow junction depth of 14.9nm at a background doping of 5×1018/cm3, and a sheet resistance of 758Ω/sq. Figure 3 shows that the XJ/RS results from SPEG processes applied to various types of implanted wafers can meet the ITRS specifications for the 65nm node, and the activation level is also compatible with 45nm needs. The SPEG results in Fig. 3 include B implants annealed at 650°C for 5 sec, and BF2 implants and BF3 implants annealed at 650°C for 20 sec. The solid black line is the profile expected for a box-shaped B-doping profile with 3.5×1020/cm3, the limit expected for electrical activation of B dopants through SPEG [14]. Figure 5b shows cross-sectional TEM images of the silicon after SPEG is complete. The region that was amorphous has crystallized and is defect-free, but EOR defects are evident near the location of the original amorphous-to-crystalline interface.


Figure 5. a) SIMS profiles of A) as-implanted and B) SPEG-processed boron distributions (using a Mattson RTP system). b) TEM pictures of the SPEG-processed samples: EOR defects (consisting of {113} defects) are located 55nm below the surface (upper, brightfield image); the surface region is fully recrystallized and defect-free (lower, HREM picture).
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The challenges for SPEG mainly relate to process integration and residual defects. One concern has been the effect of thermal cycles after SPEG on the electrical activation. Although SPEG can activate up to ~3.5×1020/cm3 for B-doping, this level is metastable, and high-temperature processing (T>750°C) after the SPEG step can deactivate the dopants [15]. The correct scheme for integration of halo and deep source/drain implants is needed; this may require the use of a disposable spacer scheme, where the SPEG process is conducted as the last implant/anneal process before the silicide.

It has been shown that SPEG-activated dopants can survive low-temperature anneals needed for the formation of NiSi, which is likely to be the silicide used in CMOS at and beyond 65nm [15]. The impact of the residual damage that is not removed by SPEG needs further investigation. Although junction leakage may be less significant in advanced devices, the implantation process may also introduce some damage in the gate dielectric, and it is not clear whether this damage can be annealed sufficiently by the low process temperature of SPEG. Further optimization of these aspects will be needed before SPEG can be accepted in manufacturing.

Conclusion

As the 65nm node draws nearer, the need for improved performance in USJ formation is stimulating focus on annealing technology. As with many semiconductor manufacturing techniques, there is enormous pressure to stretch the capability of existing approaches as far as possible to preserve the benefits of experience and to adopt a conservative approach. This means that progressive reductions in spike-anneal peak widths, in combination with advanced implant engineering techniques, are most likely to provide robust solutions for 65nm manufacturing.

For the 45nm node, new methods such as millisecond annealing and SPEG are being investigated. In millisecond annealing, the problems of pattern-induced temperature nonuniformity, thermal stress effects, and materials compatibility need far more research. For SPEG, the issues with residual defects and process integration schemes require resolution. It is possible that even in the 45nm era conventional RTP may provide the safest path forward. Beyond the 32nm node, even more sophisticated approaches may be needed. For example, the best performance in XJ/RS shown comes from a UHV-RTCVD approach, in which the junctions are formed by depositing a heavily doped SiGe film [16]. This example demonstrates the very high activation levels that can be attained when dopants are incorporated in silicon during crystal growth processes.

Acknowledgments

The authors would like to thank D.F. Downey and E.A. Arevalo of Varian Semiconductor Equipment Associates for helpful discussions and for supporting development efforts; and F. Cristiano and N. Cherkashin of LAAS-CEMES/CNRS in Toulouse for the TEM pictures.

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Paul J. Timans is director of technology, RTP Products Business Unit, at Mattson Technology Inc., 47131 Bayside Parkway, Fremont, CA 94538; ph 510/492-5992, fax 510/492-5911, e-mail [email protected].