Technology News
04/01/2004
Via-customized ASICs make e-beam direct write faster and feasible
With the cost of photomask sets pushing beyond $1.5 million for leading-edge processes, efforts in direct-write lithography are on the rise. But the wafer-throughput speeds of tools remain excruciatingly slow — even for low-volume prototyping of new ICs. For instance, customizing just the metal-routing lines in a single interconnect layer on complex, cell-based ASIC designs can take up to 20 hours using electron-beam direct write and 200mm wafers.
But now there could be a way to dramatically break the bottlenecks in e-beam direct-write technology for structured ASICs, and it doesn't require major changes to the tool or process. A via-customization technique developed by startup eASIC Corp. promises to cut direct-write throughput times to about an hour or two/metal interconnect layer in structured ASICs, says the five-year-old company in San Jose, CA.
The trick is in the eASIC chip architecture, which combines two different customization approaches from field-programmable gate arrays (FPGAs) and standard-cell ASICs. From the FPGA arena, the eASIC architecture employs bit-stream and lookup tables in the ICs to define logic or memory functions. From the ASIC arena, the architecture uses top-level metal interconnect layers to customize the routing of functions. But unlike conventional ASICs, the customization of interconnect is performed only with via structures between the sixth and seventh layers of metal. The architecture provides higher logic densities than FPGAs and lower development costs than mask-programmed structured ASICs, according to privately held eASIC.
"You only have to customize one via layer and not two or three layers of metal," explains Ze'ev Wurman, VP of software at eASIC. "Suddenly a breakthrough is possible because the entire customization of routing can be done with e-beam machines and vias without making photomasks for those layers."
 E-beam via programming is 10× faster than direct write of entire metal interconnect. |
Customizing routing with vias instead of interconnect lines cuts e-beam direct-write times down to one or two hours vs. 10–20 hours for an entire layer of metal interconnect, Wurman estimates. "Vias are different animals. They are tiny compared to metal lines. Vias are generally less than 1% of the die area, and more than that, they are a fixed size compared to metal lines."
If a "shaped beam" machine is applied, the direct-write process could be further sped up with e-beam exposures that exactly match the via's size and shape, Wurman adds. With two metal layers involved in the via-customization technique, up to 40 hours of direct-write throughput time could be cut down to as little as two hours. "You won't want to manufacture Pentium chips with this because of the need for high volume, but for reasonable quantities, the throughput suddenly becomes bearable."
The use of e-beam direct write to customize structured ASIC chips adds about $1000/200mm wafer, according to eASIC. "We've gotten those kinds of quotes from foundries, which have e-beam tools. The wafer cost goes from the range of $3000 to $5000 up to $4000 to $6000 with the extra cost, but it also eliminates the NRE [non-recurring engineering] cost for ASICs," says Wurman, referring to the price of reticles and development time, which he estimates as up to $30,000 for interconnect-layer masks in advanced processes. In addition, the direct-write routing of ASICs will enable wafer fabs to produce multiple chip designs on a single wafer and "perform just-in-time manufacturing based on customer demand," says the eASIC vice president.
The basic eASIC architecture has been licensed to STMicroelectronics and Flextronics Semiconductor. Maskless customization of eASIC devices has been tested and implemented in 130nm technology by an unidentified integrated device manufacturer, says eASIC, which is now hoping to convince dedicated foundries to make available the technology using their e-beam machines.
If maskless via customization catches hold, the technology could be a significant boost to e-beam tool suppliers, which are still waiting for wire-direct applications to emerge in commercial wafer fabs. "But I'm still skeptical," admits analyst Risto Puhakka at VLSI Research in Santa Clara, CA. The research firm estimates that e-beam tool shipments represented just $53 million in revenue in 2003. Those systems cost up to $8 million apiece, and Puhakka believes only five to seven e-beam direct-write machines are shipped each year. He adds that throughput and cost of tools "has worked against e-beam," but via customization could help solve one of those problems — speed.
Top beneficiaries of via-customized ASICs would include e-beam tool leaders Hitachi, Leica, JEOL, and Advantest. A joint venture in Japan, called E-Beam Corp. (backed by Tokyo Electron Ltd., Ebara Corp., and Dainippon Screen Mfg. Co. Ltd.), could also get a boost since the new company is developing a low-energy e-beam system, employing a character-projection method for repeatedly writing fixed patterns directly on wafers.
Applied details low-k technology development
Applied Materials recently outlined its timetable for development of low-k dielectric films, including a second-generation product that is claimed to overcome a classic problem of porous low-k films: decreased hardness as the k value decreases.
Applied representatives made their case for volume production, highlighting the certainty of the process — including integration and packaging — as well as collaboration efforts. Eight chipmakers were on hand at an event in San Francisco to present end products made using Applied's Black Diamond low-k dielectric film.
Integration of porous low-k products has been greatly slowed by decreasing hardness as the k value falls, making the film more fragile. Next-generation Black Diamond technology helps maintain hardness by managing pore size and pore distribution — the real issues, according to Farhad Moghadam, group VP, Dielectric Systems and Modules Group at Applied.
According to Ken MacWilliams, CTO/.chief marketing officer, Dielectric Systems and Modules, developing the second-generation low-k film (k~2.4) is at the top of the company's priority list. It would have to be ready by 2005–2006 to meet ITRS requirements. Moghadam said that CVD technology by itself (which is used to produce the material) is extendible down to k = 1.9.
 Low-k reduction roadmap. (Source: Applied Materials) |
Moghadam further explained that the second-generation material can be used without incurring process flow changes, and he emphasized that the tool platform is extendible; re-engineering will not be needed.
First-generation Black Diamond (k<3.0) will be used to about the 65nm node (there is some overlap between generations/.nodes), with the second generation being available sometime around 2007 and seeing the industry through to at least the 45nm node. The integration and circuit-performance benefits sweet spot for low-k will be at values <2.4, noted MacWilliams.
So far, feedback the company has received from end users is that its second-generation low-k material at 65nm will work with end users' packaging and integration requirements. Moghadam reiterated that the key is having a low-k material that is compatible with the same CMP, ECP, and barrier seed processes that have been used with FSG.
John Yue, TSMC North America, VP of technology, said that the current challenges with low-k and packaging at 130nm and 90nm have been overcome, and he expects that learning at 90nm can be extrapolated to 65nm. Essentially, the same type of low-cost, low-stress assembly equipment will be available. Ronnie Vasishta, VP, technology marketing and coreware engineering at LSI Logic, added that there was a large process window making new packaging equipment and materials unnecessary — only slight modifications are needed.
Also of interest is the future of CMP. David Bennett, director of strategic equipment technology and alliances at AMD, stated that the company is using its automated precision manufacturing technology to customize the plating process and manage copper overburden, essentially optimizing copper polishing over the entire wafer. The company has no plans to use other technologies in the near future.
With respect to barrier films, Bennett briefly noted the company is evaluating ALD with Applied and other companies, as well as direct-plating technologies for use at the 65nm node.
Purdue engineers develop quick way to prototype microchips
Purdue U. researchers have developed a new method to quickly and inexpensively create microfluidic chips — analytic devices with potential applications in food safety, biosecurity, clinical diagnostics, pharmaceuticals, and other industries. Microfluidics involves manipulating minute quantities of liquids in a chip device.
"This [development] brings the design and manufacture of these devices within reach of scientists in many laboratories, who can now easily test their ideas and conduct research within a typical laboratory setting," said Michael Ladisch, professor of agricultural and biological engineering and biomedical engineering at Purdue, West Lafayette, IN, in a Purdue statement.
Ladisch, graduate student Tom Huang, and Ladisch's team have developed an alternative to photolithography that uses materials easily acquired by any research laboratory, including glass microscope slides, tweezers, thin glass fibers such as those found in glass wall insulation, and a flexible polymer called PDMS that is available from most scientific supply companies.
"This whole device can be developed and in operation in less than two hours," Ladisch said. "Tools like this that take a lot less time to make and that can be manufactured in any lab are going to speed up the rate of research."
The new chip assembly method involves placing a fine fiber — approximately one-tenth the width of a human hair — on a glass slide and covering it with a small square of the polymer PDMS. The polymer flexes slightly over the fiber, creating a small channel on either side of the fiber, much the same way that a sheet of plastic wrap placed on top of a pencil would bend, making two channels running the pencil's length. A small amount of pressure applied with a finger is enough to cause the PDMS to stick to the glass slide.