Probing the issues for Cu/low-k wire bonding
04/01/2004
The introduction of low-k and ultralow-k dielectric films in copper-interconnect structures presents serious challenges in advanced device test, assembly, and packaging. Low-k films support higher circuit speeds and enable smaller feature sizes by increasing the insulation capability around copper interconnects, but compared to previous generations of silicon-dioxide dielectric layers, the new materials have substantially weaker mechanical properties and reduced thermal conductivity. Fragile low-k materials increase the risk of damage to finished devices in wafer probe test and high-speed final assembly processes. Experiments on different pad structures determine optimal structures and other factors for improved process robustness in probe test and wire bonding.
As 90nm technology ramps into volume production and R&D efforts target the launch of 65nm wafer processes in 2007, the need for copper metallization, combined with the use of low-k dielectric layers, becomes a critical challenge in all phases of semiconductor manufacturing, but especially in final assembly plants. Previous process generations, using silicon-dioxide (SiO2) insulators in interconnects (with a dielectric constant k = 4.2), represent the standard against which new processes are compared. Because of its high strength and fracture toughness, SiO2 provides ease of manufacturing.
Unfortunately, every low-k material in development has significantly reduced fracture toughness. Replacing SiO2 with a lower-k dielectric requires utilization of fragile materials with substantially weaker mechanical properties and reduced thermal conductivity. High-speed, demanding semiconductor assembly processes, wafer probe, and wire bonding generate significant stress levels. Compounding the situation has been the simultaneous introduction of copper interconnects and ultrafine-pitch pad layouts, which also complicate test and final assembly processes.
To contrast the design of pad structures and analyze tradeoffs in packaging materials and processes, designed experiments (DOEs) were conducted with 10 separate wafer designs. The DOEs demonstrated significant differences in bondability, and involved the two main types of low-k dielectric materials: chemical vapor deposited (CVD) inorganic films and spun-on polymer organic films.
Optimally designed structures provided significantly more robust processes. Focused ion beam (FIB) analysis for cross-sectioning die after wire-pull and ball-shear testing did not show any hidden mechanical failures. The DOEs covered results from wafer probe tests and tradeoffs and optimizations for capillary and wire materials.
Low-k's growing momentum
IC performance and cost propelled the development of low-k dielectrics in wafer processing. New low-k materials offer increased insulating capability which, when combined with copper technology, enables higher-speed circuitry (improved performance). With copper and low-k interconnects, costs can be optimized by packing more circuitry on a die with finer lines and reduced feature sizes. Additionally, fine-feature technology creates die sizes that require more input/output contacts than permitted with a normal peripheral I/O design layout, often referred to as pad-limited designs. Wire bonding over active circuitry on copper/low-k metallization layers is often required for these designs because it improves utilization of available silicon real estate.
As chipmakers race to market with products built using next-generation process technology, lower dielectric constant between interconnect layers becomes imperative. In the past year, initial production of 90nm technology and low-k ICs began at a number of device manufacturers. Low k is generally defined as k value <3.0, which can be reached with inorganic, organic, or hybrid films. They are deposited by CVD or by spin-coating the wafer. Fluorinated silicon glass (FSG), a widely used material in some 130nm processes, offers a k factor of 3.6, which is not considered low k. There are two competing process technologies: CVD carbon-doped oxides (SiOC) and the organic spun-on polymer dielectrics [1]. Applied Materials' Black Diamond is an example of the former and Dow Chemical Co.'s SiLK is an example of the latter.
Key advantages of the polymer include its extensibility, good dielectric characteristics, and proven well-characterized materials. The dielectric constant of common polymers ranges from k = 2.5–2.8. The main challenges of polymers include weaker mechanical properties than oxide, reduced thermal stability and conductivity than oxide, and potential outgassing with higher gas permeation [2].
The carbon-doped oxides fit well into normal wafer-fabrication process flows and have better hardness, elastic modulus, thermal conductivity, and lower coefficient of thermal expansion (CTE) than polymers. However, they are not considered to be as extensible as the spin-on dielectrics (SOD). Applied's Black Diamond SiOC has k = 2.8. Air has a k value of 1.0; therefore, to further reduce the k value of films, a material's porosity must be increased, but this will further degrade the mechanical properties.
Recent developments have been made in the hybrid sector. Many customers are going forward with hybrid integration schemes that employ both polymers and carbon-doped oxides. The hybrid approach is complementary because the polymers help protect the carbon oxide materials from via poisoning and etch damage, while the oxide materials provide added strength to the dielectric stack in the hybrid composite structure.
Assembly challenges with low k
The primary goal of backend manufacturing processes is to assure device reliability by preserving the integrity of the complex stack of dielectrics and metals from the silicon circuitry to the bond pad.
Mechanical strength and thermal compatibility are critical parameters for successful integration of low-k dielectrics in multilevel Cu interconnects. During the life of the device, mismatched CTE transmits strain to the weaker material, which may fail prematurely. Hardness and elastic modulus are good indicators of whether a material can survive test, wire bond, and packaging processes, and provide good long-term reliability. Table 1 shows the mechanical properties of SiO2 and common low-k dielectrics. The great differences in elastic modulus and CTE show significant low-k dielectric challenges. New techniques, specially configured equipment, and optimized process development are required to achieve the levels of manufacturability that the industry demands.
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Most low-k dielectrics are soft and spongy, with the polymers even more so than the CVD materials. During wire bonding, both the wire (ball or wedge) and the bond pad deform together, forming the bond. The soft layers within the structure allow the top metallization layer to cup and deflect under the ball, preventing the co-deformation necessary for bond formation [3]. Fluctuation electron microscopy (FEM) modeling, stiffening structures, and wafer design optimization will help to define and overcome the problem. In DOEs, optimized wafer design had a significant effect on wire-bonding process robustness. Optimized designs had a much larger "bond window," defined as the region where defect-free bonding could occur. Other designs, with different via structures or underlying layers, had significantly fewer defect-free cells and were more susceptible to peeling and pad damage.
 Figure 1. FIB analysis of probe damage. |
It was found that spin-on materials are more susceptible to cracking, and the organic material within them may contaminate the interconnect, leading to degradation. Silicon foundries have acknowledged that spin-on material problems, such as thermal stability and mechanical strength, will be major challenges as technology advances. But many believe that neither spin-on nor CVD low-k dielectric materials truly satisfy all of the electrical, chemical, mechanical, and thermal requirements, and that integrated combinations of the two will be necessary.
Wafer probe optimization
The probe tip damage to pads was quantified to determine whether minimizing it would improve bondability. Figure 1 shows an example of the damage that occurred on a probed bond pad.
 Figure 2. Probe marks from new radiused-tip design of a) initial touch-down cycle and b) after 1600 cycles. |
A new type of radiused-tip wafer probe pin with a lower force/displacement has been developed and tested. This design, used on a new card called K&S DuraPlus, creates smaller and more accurate probe marks. Figure 2 shows probe marks from the new pin after the first cycle and 1600 cycles later. Measurement of the probe marks demonstrates that they have maintained their size and consistency. The pin can maintain probe marks within a 25 × 30µm area and exerts only 1.5g/mil of over-travel. It is suited for rectangular pad designs that separate probe marks from the bond area, or for staggered, tri-, or quad-tiered designs that may have bonds over active circuitry (BOAC). low-k dielectric applications are now under test.
Pooling resources for DOEs
Combining resources and specialists, K&S collected data from 10 wafer designs as part of a collaboration [4]. These wafers were produced and bonded with metallization described in Fig. 3. The five wafers, shown as the "L-type," in the figure, had peripheral vias and passivation directly under the bond pad. The "R-type" wafers had a central via. Types 1 and 2 wafers had slightly different low-k/Cu metal directly below the pad. Type 3 wafers had an FSG dielectric. Type 4 had two low-k/Cu metal layers (1 extra) and Type 5 had three low-k/Cu metal layers (2 extra). The same 16-cell ECHIP DOE (based on software from ECHIP Inc.) was run on all 10 wafer combinations.
 Figure 3. Basic two-level Cu/low-k film stack with passivation directly under Al pad (L-type) and no passivation under Al pad (R-type). |
Contrast analysis was used to determine the statistical significance of structural differences in the wafers on robustness of the wire-bonding process. Table 2 shows a summary of the number of cells in each 16-cell DOE without failures. It's clear that the L column, peripheral via, was the best structure, based on the results. The FSG dielectric Type 3 significantly outperformed the low-k dielectric treatments. Although FSG is not a low-k dielectric, the combination of Cu and FSG provides good performance and should be considered for designs where its performance is acceptable based on manufacturability.
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One other unexpected effect was that additional layers of dielectric/metal actually improved performance (treatments 4 and 5). FEM analysis later confirmed these results and explained that the additional layers shared the load and resulted in reduced plane strain. Subsequent work using FIB analysis of structures with metal lift and peeling determined that, in many cases, the defects observed after pull testing were not in the as-bonded samples and were artifacts of pull testing. Pull-testing small-diameter ball bonds must be critically controlled and understood, or invalid conclusions may be reached. As ball bond pitch moves below 40µm, it is likely that the pull test will become less important and that shear strength will be considered the only valid measurement technique [5].
Materials optimizations
DOEs have shown that optimization of the capillary and wire is beneficial for low-k and pad-sensitive applications, such as BOAC. A new capillary design, called Sigma, showed improved process robustness with sensitive materials when compared to a standard cap. Ultrasonic transducers, although they are designed to vibrate in the y direction, actually generate displacement in the x, y, and z directions, a result of small asymmetries and manufacturing tolerances. In the Sigma design, a ring is cut in the upper portion of the capillary, which increases the movement at the tip of the cap but with less vibration. This isolates and eliminates the z displacement, while amplifying only the y component of the ultrasonic amplitude. As a result, less z strain is generated within the pad structure. Figure 4 shows the Sigma capillary design.
 Figure 4. Sigma capillary in action. |
Wire developments for low-k and ultrafine-pitch devices have focused on 4-9's wire alloys (99.99% Au). These alloys exhibit improved long-term reliability, and stronger and stiffer mechanical properties (as wire diameter is smaller than in the past). They also exhibit excellent ball formation properties for bonding on small bond pads [6].
Conclusion
Assembly of Cu/low-k dielectric devices represents a new challenge to backend semiconductor manufacturing. All of the critical manufacturing processes must work with frontend design functions to develop robust designs and processes that meet the established, exacting yield and productivity standards. Wire bonding will meet the required challenges. New machines and controls, such as the K&S Maxµmplus, which are capable of achieving the low-impact, low-stress requirements of low-k materials, will be required for this task. Specially tuned ultrasonic transducer and capillary combinations, such as the Sigma capillary, will enable high-strength bonding without generating the z-axis strains that damage delicate chip structures. High-reliability wire alloys, such as the AW-66, will produce ultrafine pitch bonds with excellent long-term reliability.
Acknowledgments
Black Diamond is a trademark of Applied Materials Inc. SiLK is a trademark of Dow Chemical Co.
References
1. M. Gotuaco, P.W. Lee, L.-Q. Xia, E. Yieh, "The Case for CVD Low K," Vol. 1, Issue 1, Applied Materials Update 2002.
2. D.C. Frye, "Packaging Challenges for Advanced Low K for Flip Chip and Wire Bond," 9th Annual K&S Semicon West Tech. Symposium, July 2002.
3. L. Levine, "The Trend Toward Copper with Low k Layers Continues," Chip Scale Review, Jan.–Feb. 2002.
4. J. Brunner, F. Keller, T. Pan, "Optimization of Wire Bonding Over Cu-Low K Pad Stack," Proc. IMAPS, November 2003.
5. V. Sundararamen, D.R. Edwards, W.E. Subido, H.R. Test, "Wire Pull on Fine Pitch Pads: An Obsolete Test for First Bond Integrity," Proc. ECTC 2000.
6. I. Singh, L. Levine, J. Brunner, "Reliability Ground Rules Change at <50µm Pitch," Proc. IEMT 2003.
Bob Chylak earned his dBSEE from Penn State U. and holds two patents. Chylak is VP, packaging and process integration, for Kulicke & Soffa Industries Inc., 2101 Blair Mill Rd., Willow Grove, PA 19090; ph 215/784-6446, fax 215/784-6284, e-mail [email protected].
Frank Keller received his BS in business administration and his MS in industrial engineering from Penn State U., and his BSEE from Spring Garden College. Keller is manager of process R&D at Kulicke & Soffa.
Lee Levine received his bachelors in metallurgy and materials science engineering from Lehigh U., Bethlehem, PA. He received the John A. Wagnon Technical Achievement Award from the International Microelectronics and Packaging Society. Levine holds four patents and is a senior member of the technical staff for Kulicke & Soffa's Advanced Packaging Ball Bonder Division.