Deep silicon etching used for key MEMS building blocks
04/01/2004
Etch requirements for four basic deep Si processes — bulk, precision, SOI, and high aspect ratio — are presented and contrasted. These diverse processes are needed to satisfy today's MEMS manufacturers. Future devices will extend these building blocks even further; higher rates, better uniformity, smoother sidewalls, and higher aspect ratios are all anticipated.
Microelectromechanical systems (MEMS) involve movement on a chip — cantilevers, membranes, sensors, mirrors, gears, motors, resonators, valves, pumps, liquids, etc. What links these together is a common fabrication technique known as micromachining. Silicon's well-known mechanical and electrical properties and commonality with the mainstream IC industry make it the material of choice for micromachining. Wet etching silicon benefits from being fast and low in cost; however, it is either isotropic or reveals crystal planes as facets within the silicon, restricting its use to specific manufacturing applications such as the fabrication of micronozzles for ink-jet print heads. (Isotropy is a problem because of CD loss going 100µm down while simultaneously going sideways 100µm.) Dry etching overcomes these restrictions, allowing vertical sidewalls at geometries governed by standard photolithographic masks. As an example, the moving mass of capacitive accelerometers is often wet etched, but more accurate dimensional control is available from dry etch that will allow overall device dimensions to shrink.
Deep Si etching
The most commonly accepted method of deep Si etching is based on the Bosch gas-switching technique [1]. The process relies upon repetitive switching between an isotropic etch plasma and a plasma that deposits a polymeric passivation layer. SF6 is the usual choice for the etch gas because it can release its six fluorine atoms with just 20eV of energy. These fluorine atoms then spontaneously react with the Si, forming volatile SiF4. Theoretical calculations show that etch rates up to 20µm/min on patterned 150mm Si wafers with ~15% open area require a plasma chamber pressure >30mtorr, an SF6 flow rate >400sccm, and RF powers in the kilowatt range.
For high-rate polymer deposition, the F:C ratio in the plasma should be ≤2:1, thus ruling out CHF3 and C3F8 in favor of C4F8 (also a common additive to oxide etch plasmas). The polymer-deposition plasma provides an adjustable means of sidewall passivation and a high net selectivity to masking materials such as photoresist or silicon dioxide. Gas switching is required for the combined SF6 and C4F8 process because the side reaction CF2 + 2F Æ CF4 removes both etchants and passivants from the plasma, producing a scalloped but net anisotropic wall profile and conveniently operating at room temperature. The deposited polymer is easily stripped at the end of the process using an O2 plasma.
 Figure 1. Generic aspects of a typical plasma source for deep Si etching. |
Capacitive RF coupling, used for conventional reactive ion etching (RIE) at high pressure, cannot deliver enough RF power for gas dissociation without inducing very high bias voltages. Conversely, an inductively coupled plasma (ICP) becomes nonuniform at high pressure when gaseous diffusion is slower and power coupling becomes localized, meaning that large fractions of the gas are undissociated. The solution for deep Si etching is combining an upstream source, where gas is fed through a small, high-RF power, inductive region, and a downstream reaction chamber containing the wafer with low-RF bias power.
 Figure 2. Si etch rate matrix for blanket 150mm wafers. |
Permanent magnets may be added to reduce electron losses to the chamber sidewalls, thus enhancing gas dissociation as well as electromagnets to optimize RF coupling within the source and shape the resulting plasma to compensate for any nonuniformities in etch rate. Trikon's DSi process module has been designed in this way. Figure 1 shows generic aspects of a typical plasma source for deep Si etching.
Etch process flow
Figure 2 shows the results from a matrix of etch-rate measurements on blanket (unpatterned) 150mm Si wafers. Wafers (150mm Si) were added for consistency testing and showed that repeated process conditions gave agreement on etch rate to within 1%. The data show the influence of source power and SF6 flow on etch rate: at 2.5kW and 900sccm, a rate of ~5µm/min is achieved. Also evident are the weaker effects on etch rate of chamber pressure and bias power (at least in the absence of polymer-deposition steps). The observations are consistent with a chemically driven reaction between F atoms and the Si wafer surface. Similar experiments measuring the blanket deposition rate of polymer show that high pressure and C4F8 flow favor polymer deposition. It is likely that CF2 radicals act as the precursors to the polymer film.
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There is a diverse set of requirements to satisfy the broad range of MEMS devices being fabricated and planned. The situation can be simplified by reference to a generic suite of etch process types. The table summarizes the contrasting etch requirements for four process types.
Bulk etching
 Figure 3. 200µm feature etched at a) high rate, and b) close up showing ~220nm-deep sidewall scallops. |
Some MEMS devices require the removal of large volumes of bulk Si substrate. Pressure sensors, for example, can be made by etching deep holes from the rear of the wafer to form thin diaphragms at the front face. Other devices require through-wafer etches that either penetrate the back face or stop on a back coating. A feature of the Bosch process is that it can be difficult to obtain high etch rates while retaining a near-vertical profile with smooth walls. The highest etch rates normally compromise wall angle by a few degrees or so. Fortunately, bulk etches of this type rarely require vertical walls. Figure 3 shows a 200µm-wide feature with a 91.8° wall profile that has been etched at a net rate of 12.4µm/min.
Precision etching
Precision etch processes are designed for smaller, more critical parts where profile verticality and sidewall smoothness are paramount. MEMS devices requiring this approach include MOEMS (for high-reflectivity mirrors) and embossing die. The absolute etch rate is less important than the need to control the etch rate uniformity. Etchant density is reduced above the areas of high consumption, so the etch rate intrinsically rises toward the edge of the wafer. Uniform etching requires corrections to the plasma or ion bombardment profiles. The magnetic field of the DSi is used to concentrate bombardment toward the wafer center through separate control of the field strength and geometry. Etch rate uniformities in the range ±1.0–2.5% are routinely obtained on wafers up to 200mm.
 Figure 4. Typical correlation between net etch rate and scallop depth for features 1.7µm wide (~6:1 aspect ratio) and 200µm wide (~1:1 aspect ratio). |
Sidewall roughness is caused by the depth and length of the scallops that in turn are mainly a consequence of the relative etch and polymer-deposition step times. Figure 4 shows the strong correlation between net etch rate and scallop depth (normally measured at the third scallop from the mask). Data is shown for 1.7µm- and 200µm-wide features. Aspect ratio-dependent etching (ARDE), a common feature of the Bosch process, is responsible for the variation in etch rate with feature size. Figure 5 shows an example of a 100µm-wide feature etched at 5.5µm/min with scallops <30nm in depth.
SOI etching
The most advanced MEMS devices contain detailed moving parts, such as cantilevered masses for accelerometers and gyros, tilting mirrors, vibrating resonators, valves, pumps, and turbines. Many of these components are initially defined by deep Si etches from the front face of the wafer, then are released from the substrate by undercutting with a lateral, isotropic etch. The approach is referred to as surface micromachining. Buried layers are used as stop layers for the anisotropic etch and to confine the isotropic release etch. Silicon dioxide is a convenient buried-layer material because of the high selectivity that can be achieved to Si etches and the availability of SOI substrate wafers at most wafer sizes.
 Figure 5. Precision etching of a) a 100??m feature with b) scallop depth <30nm. |
The initial deep Si etch to the buried oxide layer is not straightforward. The oxide charges up with positive ions at the endpoint — exacerbated when features of varying widths are etched simultaneously, whereby ARDE means that the wider features must be over-etched while narrower features catch up. At the same time, the charging causes sideways etching across the interface; notching from this mechanism makes subsequent deposition onto the sidewall more problematic. A solution is to pulse the RF bias either throughout the entire etch or as the oxide layer is approached. Using an appropriate time constant, the power-off periods provide time for electrons to discharge the insulating surface. Figure 6 shows an SOI etch process for a 1.9µm-wide feature where the profile is 90°, the etch rate is 3.7µm/min, and the notch depth is <100nm. The etch rate uniformity on this wafer was ~±1.5%.
 Figure 6. SOI etching a) with continuous bias power and b) with pulsed bias power. |
Due to ARDE, features ≥20µm in width experience over-etches typically on the order of 90%; despite this, the notch depth is consistently around 100nm irrespective of the feature size in the range 0.8–20µm. Bias pulsing thereby provides a high degree of process latitude for SOI applications.
High aspect ratio
Deep Si etches are often required to cope with high aspect ratios. Examples of MEMS devices with high aspect-ratio features include gyroscopes and hard disk-drive heads. They are also being used in the development of next-generation, high-density interconnect solutions that migrate packaging processes to the wafer level. The main problem at high aspect ratios relates to plasma transport into and out of the features: etchants that have difficulty getting to the etch interface (assisted by ions to break through the polymer layer) and by-products that are restricted from exiting the hole. Ion collimation intrinsically limits the aspect ratio to about 50:1 at normal plasma pressures. In addition, subtle variations in mass transport with feature depth can alter the profile over the course of the etching. Generally, it is the etch component that preferentially reduces with depth, leading to excessive polymerization and a narrowing of the feature. Equipment makers have devised hardware and processes that gradually increment the process conditions with etch depth, which can be set up to compensate for variations in mass transport.
Figure 5b is an example of a process designed for 200mm wafer-level packaging. The feature is 2.5µm-wide with an aspect ratio of ~21:1. The feature was etched at 3.5µm/min and has a uniformity of ±1.5%. The >89° profile and ~30nm scallop size allow subsequent lining with dielectric material.
Conclusion
High-volume MEMS manufacturers, operating mainly within the automotive and IT/entertainment sectors, will drive the demand for production-worthy deep Si etch solutions over the next few years.
Deep Si etches are key building blocks in the fabrication of MEMS devices. The four processes described illustrate the diversity of dry etches required — and all are needed, with perhaps more variants in the future. A common theme is profile control. The high-rate etches tend to go re-entrant as depth increases (too much etching relative to polymer deposition); high aspect-ratio features tend to taper the other way with depth (too little etching relative to deposition); and SOI etches can be used where a notch-free profile needs to be maintained at the buried oxide stop layer.
The process technology needs to diversify, yet become more stable and reproducible so that reliable, high-volume production can be reached. In particular, etch rate uniformity needs improvement: aspect ratios need to increase (with tight CD control across wafer), and generally, etch rates need to be higher (for higher throughput and lower cost of ownership). High-rate etches are becoming more necessary because many etches are through-wafer (at least 400µm), and the longer the etch time, the higher the CoO. Dry etch will become more prevalent because it is inherently anisotropic.
Acknowledgment
DSi is a registered trademark of Trikon Technologies.
Reference
1. F. Laermer, A. Schilp, US Patent 5501893, 1996.
Dave Thomas is etch product marketing manager at Trikon Technologies, Ringland Way, Newport, Wales, UK, NP18 2TA; ph 44/1633-414027, fax 44/1633-414180, e-mail [email protected].
Market trends
The MEMS market has continued to grow at around 20–25% CAGR despite the recent downturn in the global semiconductor business. Currently, MEMS is highly fragmented, with about 400 manufacturers worldwide. The future is likely to see significant consolidation through a combination of acquisitions, mergers, and technology licensing. Over time, the number of producers will inevitably decline but the overall device volume is expected to rise.
At present, the volume markets are primarily in IT/entertainment (ink-jet heads, read-write heads, and data projection) and automotive (accelerometers, gyroscopes, and pressure sensors) sectors. The table shows the top 15 MEMS manufacturers based on estimates of their 2002 device revenues.
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Recent data indicates that the joint total accelerometer/inertial sensor device market was valued at ~$734 million in 2002 and that this will likely rise to ~$1.2 billion by 2005 with ~90% of this market being automotive, according to Yole Development.
Potential "killer applications" exist in telecom (MOEMS, RF MEMS), biological (DNA chips), and medical (fluidics) sectors, but these are likely to take up to five years to reach production volume.