Using a biased-ICP reactor for PR strip and Cu barrier removal
04/01/2004
A 2-in-1 integration scheme — in which the barrier removal and photoresist strip are done in situ following dielectric etch — is proposed. Photoresist stripping and barrier removal on SiLK, porous SiLK, and LKD-5109 dielectric materials were evaluated with a process developed on blanket films and later optimized on patterned wafers. Pattern wafer performance was evaluated on single- and dual-damascene structures using cross-section SEM and TEM.
Continuous scaling of semiconductor IC manufacturing along with the requirement for reduction of signal delays have resulted in the introduction of copper interconnects and low-k dielectric materials in the backend-of-line. These new materials profoundly affect process schemes that will have to be employed to ensure integration success.
Dielectric patterning is one of the essential parts of the dual-damascene process; many different schemes are currently being used for this step. Some use a 3-in-1 process, with the dielectric etch, barrier-open, and photoresist (PR) strip done in situ in one chamber. Other methods employ separate chambers for low-k etch, PR strip, and barrier-open. Dielectric film compatibility comprised of profile control and k-value retention is key for success of all dual-damascene integration schemes. To address these requirements, a team evaluated the feasibility of using Mattson's Aspen III Highlands low-k strip system with an inductively coupled plasma (ICP) reactor and a biased wafer platen.
Process development for the 2-in-1 integration scheme was carried out in two phases. Initial development was done on blanket films to determine removal rate and selectivity dependence [1]. The best processes were then optimized on patterned wafers, where effects of the chemistries on dielectric integrity and overall integration were studied. In the first phase, three chemistries were selected for the anisotropic SiC barrier removal application: H2/CF4, N2/CF4, O2/CF4, and three other chemistries were selected for the resist strip process: N2/O2, O2/H2, and N2/H2. Finally, TEM, SEM, and interlayer capacitance (ILC) techniques were used to verify the viability of a 2-in-1 process.
An advanced low-k strip system featuring an ICP reactor with a biased wafer platen was used to study the 2-in-1 integration scheme. The system's reactor has an ICP source with a grounded Faraday shield. The bottom electrode was biased and operated at the same frequency as the ICP source (13.56MHz). In all experiments, barrier removal and PR strip were conducted on the Highlands system. All dielectric etch steps were done in conventional etchers not made by Mattson.
Primary screenings on blanket substrates
In the first phase of the study, experiments were carried out on blanket CVD SiC, CVD oxide, dense SiLK, and resist wafers to screen the best process conditions. The impact of gas mixture and gas composition on removal rates and selectivity was evaluated.
Three different gas combinations were evaluated: CF4/H2, CF4/N2, and CF4/O2. The CF4/O2 chemistry yielded the highest removal rate with a maximum rate of 330nm/min and also provided the highest selectivity of 2:1 for SiC:SiO2 (see Fig. 1). Even though the CF4/O2 chemistry provided the highest removal rate and selectivity, we decided not to designate a lot of process development to that chemistry as we suspected chemical compatibility issues between O2-containing chemistries and the wide variety of dielectric materials that we were planning to test. Consequently, development efforts were focused on the CF4/H2 and CF4/N2 chemistries for the Cu barrier removal process. The measured SiC:SiO2 selectivities for the CF4/H2 and CF4/N2 chemistries were 1:1 and 1.5:1, respectively.
 Figure 1. SiC/SiO2 selectivity vs. CF4 concentration. |
PR stripping with oxygen-containing and oxygen-free chemistries was characterized. Strip rates >600nm/min were obtained with pure O2, N2/O2, and O2/H2 chemistries. Maximum strip rate for the N2/H2 chemistry, an alternative for oxygen-based chemistry, was ~230nm/ min. Resist reticulation on blanket PR wafers for high H2 concentrations and long strip times was observed, but resist reticulation was not observed on patterned wafers. A possible explanation for this phenomenon is that the resist becomes fluorinated during dielectric etching and, subsequently, the incorporated fluorine aided in removal of the resist in the strip step.
Screenings on patterned wafers
In the second phase, patterned wafers were used to evaluate CF4/H2, CF4/N2, and CF4/O2 chemistries for removing a SiC barrier layer. Oxygen-based PR strip chemistries were evaluated for full 2-in-1 process integration. These tests were carried out on wafers with single-damascene, low-k dielectric trenches on blanket oxide and blanket Cu substrates. Initially, feasibility of SiC barrier removal was evaluated using the wafers with an oxide underlayer.
Integration schemes pursued for this investigation depended on the type of dielectric that was used. Chemistries used for etching MSQ-based dielectrics (LKD-5109) have high selectivity to PR; as a result, PR would remain after dielectric etching. For this application, two approaches were evaluated: 1) resist strip prior to the SiC barrier removal, and 2) SiC barrier removal prior to the resist strip. For organic spin-on dielectrics (SiLK), dielectric etching simultaneously consumed the PR mask, so evaluating integration of these organic spin-on films only encompassed SiC barrier removal.
 Figure 2. SiC removal followed by resist strip. |
For MSQ-based dielectrics (LKD-5109), there are two possible alternatives: resist-strip-first or SiC barrier-removal-first approach. Figure 2 shows a SiC barrier-removal-first followed by a resist-strip approach. This wafer had a Cu underlying film with an LKD-5109 dielectric layer, which had been previously etched in a separate system. Subsequent SiC barrier removal and PR strip were performed in the low-k strip system using CF4/H2 chemistry for SiC barrier removal and N2/O2 chemistry for PR strip. This wafer did not receive an additional wet clean prior to the SEM picture. As shown in Fig. 2, the Cu surface was clean without any residues. The dielectric sidewalls appear to be vertical. Studies were also done on the same dielectric stack using the PR-strip-first, SiC barrier-removal-last process. Profile control and residue removal, however, were not acceptable for the SiC barrier-removal-last process.
 Figure 3. Single-damascene SiLK structures used for ILC measurements. |
Figure 3 shows a cross-section TEM picture from a SiLK single-damascene stack on oxide after the SiC barrier removal using CF4/H2 chemistry. It can be seen that the SiC barrier was successfully removed, and the dielectric and barrier sidewall profile were maintained. The TEM picture shows some hard-mask rounding, which is attributed to both the dielectric etch and the SiC removal processes. As noted earlier, PR strip was not required for this process as PR was entirely consumed during the previous dielectric etch step.
 Figure 4. Completely processed damascene porous SiLK stack. |
SiC removal studies on porous SiLK were also performed. Figure 4 shows a TEM picture of a wafer subsequent to Cu metallization and CMP. This wafer had a spin-on hard mask instead of the oxide hard mask that was used for the wafer in Fig. 3. The SiC barrier removal process was successful and sidewall profiles maintained.
ILC measurements
ILC measurements were performed on single-damascene (SD) test structures to study the impact of different chemistries on the effective k value. The results of an ILC experiment on SD SiLK are shown in Figs. 5 and 6. Figure 5 compares the as-measured ILC values of a reference wafer, which did not undergo SiC barrier removal or a wet solvent clean, and other wafers, which were processed with different SiC barrier removal chemistries.
 Figure 5. Cp in function of nominal space. |
In general, measured ILC data for the CF4/H2 SiC barrier removal chemistry are somewhat lower than for the other splits. These differences could be explained by the larger contribution of the low-k film in the dielectric stack because of the hard-mask erosion/faceting (hard-mask rounding can be seen in Fig. 3). The CF4/O2 chemistry showed the highest ILC values, which pointed toward low-k-value degradation.
 Figure 6. A k-value simulation. |
A k-value simulation was performed with a RAPHAEL simulation tool. Figure 6 shows the measured capacitance (Cp) data for a wafer after SiC barrier removal with CF4/H2 chemistry (100% OE) and the Cp simulation results with k values of 2.7 and 2.7±0.2, respectively. Also shown are the data measured on a reference wafer (no processing on the low-k strip system). There was an offset between the simulated data for a k = 2.7 and the as-measured data. Wafer inspection revealed that locally the hard mask was completely removed during CMP. Thus, a possible explanation for the offset between measured and simulated data could be moisture uptake during post-CMP clean.
Conclusion
Feasibility data for SiC Cu-barrier removal using an Aspen III Highlands system were presented to test a 2-in-1 scheme with PR strip and SiC removal performed in the same chamber. Integration success was verified using blanket, single-, and dual-damascene structures on SiLK, porous SiLK, and LKD-5109 dielectric materials. ILC tests demonstrated good electrical performance and confirmed the viability of the 2-in-1 process.
Acknowledgments
Co-authors of this article are M. Stucchi, T. Conard, S. Vanhaelemeersch, and J. Van Aelst of IMEC, and R. George of Mattson Technology. Registered trademarks are Highlands: Mattson Technology; SiLK: Dow Chemical Co.; and LKD-5109: JSR.
References
1. G. Mannaert, M. Van Cauwenberghe, M.O. Schmidt, J. Van Aelst, D. Hendrickx, et al., "Resist Strip and Cu Diffusion Barrier Etch in Cu BEOL Integration Schemes in a Mattson Highlands Chamber," UCPSS 2002.
Werner Boullart, IMEC, ph 32/16-28-18-57, e-mail [email protected].