Technology News
03/01/2004
Could jet-printed plastic transistors erase lithography from display plants?
Jet-printing technology for depositing polymer-based semiconductor ink on display substrates could be ready for pilot production by the middle of 2005, now that researchers at Xerox Inc.'s Palo Alto Research Center (PARC) have successfully produced the first plastic transistor array entirely patterned with jet printing. The technology combines a modified ink-jet printer and semiconductor ink — developed last year by the Xerox Research Center Canada (XRCC) — to create thin-film transistor arrays for control of flat-panel displays (see figure).
The first plastic transistor arrays and upcoming work to produce a full-prototype display based on jet-printed semiconductors come in the final phase of a four-year project backed by a National Institute of Standards and Technology (NIST) grant and an R&D partnership between Xerox, Motorola Inc., and Dow Chemical Co.
The ultimate goal in developing low-cost jet printing of circuits is to replace photolithography and vacuum deposition steps currently used to make active-matrix displays. The hope is also to give birth to new printing techniques that could transform flat-panel display manufacturing to "roll-to-roll" processes vs. today's batch processes, explains Robert Street, research fellow at PARC in Palo Alto, CA. The roll-to-roll process could be used to make displays that roll up like a window shade and reflective displays dubbed "electronic paper," he suggests.
With material deposition and transistor patterning done simultaneously in jet printing, a cost savings of 3× to 5× is possible over lithography-based processes, Street estimates. "Transferring from a batch process to roll-to-roll processes could get you another factor of two to three in savings," says the PARC research fellow.
"Lithography is a fairly complicated process. It can take up to seven or eight different types of process steps to pattern a single layer for transistor arrays," Street says. PARC's ink-jet printer system and process was used to make an initial prototype transistor array suitable for a 2-in. diagonal display. "This is scalable, and with the present equipment, we could go up to 6 or 8 inches. There are yield issues to resolve."
By year's end, PARC scientists aim to integrate the printed thin-film transistor arrays with a reflective media to understand how the circuits can be optimized and controlled. Researchers believe the jet-printing technology could be used to make wall-sized TVs, unbreakable cellular phone displays, and roll-up computer displays. Xerox itself is particularly interested in making plastic transistors feasible for printed reflective displays, which it calls "electronic paper." This capability is being pursued by PARC spin-off, Gyricon LLC, Ann Arbor, MI.
PARC's current plastic transistor-array technology combines additive printing and subtractive processes to make display circuits. Polymer inks are jetted directly onto substrates to pattern semiconductor transistors using the additive process. In the subtractive step, other materials — such as metal and insulator films — are deposited over the entire surface and a mask is jet-printed on top. These materials are dissolved except where protected by the printed mask. Eventually, PARC hopes to create a jet-printing transistor process that is completely additive and provides the lowest cost possible with fewer steps, Street says.
A patent-pending computer vision system was created for the modified ink-jet printer to enable precise alignment of each layer. The registration of layers is achieved even if the flexible substrates deform slightly during the printing process, according to PARC. Researchers say the ink-printed plastic transistors meet all the requirements for addressing displays, including high mobility, low leakage, and stability. The semiconductor polymer is in the polythiophene family and is engineered for jet printing.
"We are halfway to the fully additive printing process," says Street, who believes this version of the technology could be ready for pilot production in about 18 months. Xerox has all of the technologies and systems for complete production lines — including print heads and materials — but "it is not our intention to become an equipment manufacturer," Street adds.
But if/when jet-printed transistor technology does hit the market, the results could be devastating to lithography suppliers, warns semiconductor equipment analyst Risto Puhakka, VP, operations, at VLSI Research Inc., which estimates that $765 million in lithography systems were shipped to display manufacturing plants in 2003, compared to $2.74 billion for IC fabs. In 2005, FPD applications will account for $1.3 billion in lithography revenues, Puhakka predicts.
"If someone comes up with something like this [jet-printing of transistors for displays], it will create big headaches for the lithography companies," he says. — J.R.L.
X Initiative sees 2004 as the year of production chips
With Toshiba's announcement that it produced the first functional silicon at 90nm using X Architecture, and UMC's release of its readiness to accept X Architecture designs for 180nm, 150nm, and 130nm processes, the X Initiative thinks 2004 will see its roadmap to production come to fruition.
 Figure 1. X Architecture cost/performance vs. Manhattan architecture. (Sources: Cadence Design Systems and X Initiative) |
Aki Fujimura, steering group member and CTO, new business incubation at Cadence Design Systems, stresses that X Architecture improves performance, power consumption, and cost simultaneously; IC manufacturers can choose which benefit is most important (Fig. 1). For example, Toshiba said its test chip had 14% less total wire length and 27% fewer vias than a traditional layout.
 Figure 2. CD uniformity results with X Architecture. |
The table shows results for various designs comparing X Architecture to Manhattan. Fujimura points to Applied Materials' presentation at the Design Automation Conference in June as another positive indicator for X Architecture's advance. The equipment supplier showed data (on design-rule test chips) on CD uniformity as measured on 76 die on a 300mm wafer (Fig. 2). For dense features, CD uniformity was 3.4% of the CD (3s = 4.9nm) and for isolated features, it was 4.3% (3s = 6.1nm).
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With the participation enjoyed by the organization throughout the design-for-manufacturing supply chain, Fujimura further points to Toshiba's pronouncement by Dr. Yoshimori that there is no longer any technical barrier to using X Architecture — it's ready for production in 2004.
Rita Glover, president and principal analyst of EDA Today, notes that insiders say no pushback is being experienced with this technology's adoption and adds, "Of course, new 65nm and 45nm processes will require further validation, just as Manhattan architectures would."