Looking forward to 65nm: Nonporous low-k dielectrics
03/01/2004
In the early 1990s, when the search started for low-k dielectrics to provide lower capacitance and improve signal integrity by reducing crosstalk between adjacent lines, process engineers wanted low-k materials to be the direct replacement of PECVD oxide (k ≈ 4). The desire was to have all process and thermomechanical characteristics the same as that of PECVD oxide, but at that time, no material (with k≤3) was available that had the desired characteristics for volume manufacturing.
Realizing the big potential for business and technology insertion, many equipment and material suppliers started new programs and the market was flooded with a variety of low-k dielectric materials. But volume manufacturing using low-k dielectrics did not happen, even though various low-k dielectrics were available. Ultimately, fluorinated silicon glass (FSG; k ≈ 3.5–3.7) was used in chip manufacturing for 0.13µm technology nodes.
So what happened? First, low-k materials were new materials, and second, many types of low-k materials were made available with different elemental compositions, structure types, and material characteristics. And third, most of the new low-k materials had enormous technical challenges regarding integration with copper; the solutions were not cost-effective for high-volume manufacturing.
Today most of the fog has cleared. Among most of the low-k dielectrics that are available, only a few have shown maturity as potential candidates for volume manufacturing at 90nm technology nodes. Clearly, PECVD films produced by replacing some of the oxygen in SiO2 by methyl groups show the widest acceptance in the industry. These films belong to a general category called carbon-doped oxide (CDO) or SiCO, and are offered by at least three different companies. These films all belong to the same category, but their microstructures are still different. ASM's Aurora film (k≤3) is deposited from dimethyldimethoxysilane (DMDMOS) and is offered on the HVM Eagle platform. It is becoming a solution for the 90nm node because of its attributes.
Going forward for 65nm technology, one idea is to have low-k dielectrics with k≤2.6, which translates to the need for porous low-k dielectrics. Many porous low-k films are available in the market. These films are either deposited by PECVD or by spin-on method involving co-deposition of a porogen; the latter is removed thermally. Again, PECVD porous films have improved thermomechanical characteristics. The smallest pore sizes and closed pores are preferred because of integration challenges.
The fundamental challenge for high-volume manufacturing of ICs at the 65nm technology node is associated with the integration of porous low-k dielectrics with copper in dual damascene interconnect structures. One of several issues to be resolved is that as the dielectric constant is lowered, the mechanical properties, such as hardness and elastic modulus, are also lowered. As these films are integrated with copper in multilayer interconnect structures, the films have a higher probability of yielding to generated stresses and loads, which result in delamination, defects, lower yields, etc. This issue is even more pronounced at the packaging stage due to higher applied loads. The effort here is to develop alternate packaging technology.
The other issue is the quality of a dielectric sidewall's structure after etching. That is, if the sidewalls have small curved surfaces — the so-called cavities resulting from the etching of porous low-k dielectrics — then PVD barrier and seed deposition is a bigger challenge as thin and smooth sidewalls and bottom coverage are needed. Even if PVD barrier film can be deposited, an increase in the via resistance of small-dimension vias needs to be addressed. For the latter reasons, atomic layer deposition (ALD) of barrier film appears attractive.
In ALD technology, it is necessary to monitor ALD precursor gas penetration into the pores of the porous low-k dielectrics and CD losses. Of course, this is mostly true for the open-pored, porous low-k dielectrics. There has been a great effort to resolve this by developing a pore-sealing technology step before ALD of film. Another challenge is related to direct CMP polishing of porous low-k dielectrics.
Yet another concern is stress-induced voiding and the reliability of the interconnect structure after copper deposition and CMP. These problems are related to the mechanical robustness of the porous dielectric, the porous dielectric-metal barrier, and the porous dielectric-barrier interfaces. The effective dielectric constant (Keff) of the integrated stack is a key issue: after integration, the dielectric constant value of as-deposited porous low-k films vs. porous low-k films should not deteriorate.
The next question is, how we can avoid the fundamental problems associated with integration of porous low-k films? A simple solution to this problem could be to use nonporous low-k dielectrics. Is this really possible for 65nm node technology? The answer is possibly, yes. The current PECVD low-k dielectrics most likely will extend in slightly modified form.
Acknowledgments
ASM, Aurora, and Eagle are registered trademarks of ASM International N.V.
For more information, contact Devendra Kumar, director of technology, ASM, 97 East Brokaw Rd., San Jose, CA 95112; ph 408/451-0830, fax 408/451-0835, e-mail [email protected].