Issue



ITRS: Increasing complexitycreates packaging challenges


03/01/2004







The 2003 edition of the International Technology Roadmap for Semiconductors (ITRS), made available in December (http://public.itrs.net), highlighted many challenges related to system-in-package issues and the increasing complexity of semiconductor products, as well as the growing interrelated nature of semiconductor design and manufacturing flows.

The ITRS, the primary coordinating document for the future technical path of the industry, is most often cited in the wafer fabrication portion of the semiconductor industry, but many of the chapters report on packaging-related topics.

Each of the 13 International Technology Working Groups (ITWGs) covers some portion of the semiconductor industry. Besides the Assembly and Packaging group, many others discuss topics related to packaging, including Design, System Drivers, Test and Test Equipment, Interconnect, and Modeling and Simulation.

Packaging's grand challenges

Each ITWG identifies its "difficult challenges," which are gathered and summarized as "grand challenges" to represent the overall situation. The grand challenges fall into two main categories: enhancing performance and cost-effective manufacturing. They are also described as being "near term" (through 2009) and "long term" (2010–2018), as shown in the table on packaging-related issues.

It is noteworthy that the near-term issues of enhancing performance are specifically related to interconnect. Copper and low-k dielectric structures on chips have created significant challenges for assembly processes because of the diminished mechanical integrity of low-k materials, which has actually delayed the proliferation of copper/low-k developments beyond the initial projected timing. The other challenge in this area is the design of interconnect. The ITRS reports that the "lack of optimization tools for interconnect/packaging architecture design makes total optimization of interconnect systems difficult." Design tools have typically addressed specific areas of design separately, but the ITRS tells us that this will no longer be adequate.

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There are more near-term challenges in the cost-effective manufacturing category than the enhancing performance category. Highly integrated designs create numerous challenges, including the lingering challenge of known good die (KGD). In system-in-package (SIP) configurations, a significant issue is the test of a variety of device types that will be designed into SIPs. These include MEMS, optical components, and other devices beyond conventional semiconductors.

Design tools appear in this set of challenges, with chip/package co-design cited as a critical area. The need for concurrent design of chips and packaging is widely known as a key to continuing to meet performance requirements, but the ITRS also calls out design cycle time as an issue that needs to be addressed.

The challenges facing the industry are not entirely technical, and the ITRS describes one of these as "responding to rapidly changing complex business requirements." A fact of the current marketplace is quickly evolving demands from customers, as well as a complex product mix. With SIP solutions emerging, this is a particular issue for packaging factories.

The long-term challenges identified by the ITRS mention packaging-related issues less frequently than the list of near-term challenges. As in the near-term challenges, though, the long-term challenge for enhancing performance is related to interconnect. With on-chip interconnect moving beyond copper/low-k systems, there will be new issues for package design and processing.

Challenges in assembly/packaging

The ITRS identified a dozen difficult challenges specifically in the assembly and packaging area. The near-term (through 2010) challenges are:

  • improved organic substrates,
  • improved underfills for flip chip on organic substrates,
  • coordinated design tools and simulators to address chip, package, and substrate co-design,
  • impact of Cu/low-k on packaging, and
  • high current-density packaging.

Two of these (co-design and Cu/low-k) appear on the list of the industry's grand challenges. Materials issues, and substrates specifically, appear in more than one of the challenges.

The long-term (2010–2018) challenges are:

  • package cost that does not follow die cost reduction curve,
  • small die with high pad count, high power density, and/or high frequency,
  • high-frequency die,
  • gaps between substrate technology and the chip,
  • system-level design capability to integrate chips, passives, and substrates,
  • new device types (organic, nanostructures, biological) that require new packaging technologies, and
  • bumpless area-array technologies (e.g., face-to-face and other 3D packages).

Several of these are related to mismatches between packaging and other parts of the semiconductor supply chain. The different rates of cost reduction for packaging and the die provide the first challenge on the list, and this situation results in inadequate profit margins in packaging to support the investment required to reduce the cost. Co-design appears again in the long-term list, as does substrate technology. For substrates, the ITRS says that production techniques will require silicon-like process technologies. Perhaps that shift is what will help to address some of the cost issues.

System-in-package updates

The ITRS is quite optimistic about SIP, reporting that "the SIP packaging concept is here to stay." The key factors driving the adoption of SIP over SOC or other integration schemes include:

  • Different IC technologies can be assembled in the same package.
  • Dissimilar die geometries (from 90–250 nm) can be integrated in the same package cost effectively.
  • Other technologies such as MEMS or optical components may be included in the same SIP.
  • Different interconnection technologies can be used.
  • Revisions or upgrades to OEM products are easily accomplished, therefore reducing the cycle time for these changes.

There are clearly challenges for continued adoption of SIP, including a need for new metrics for cost-effectiveness. Both cost/area and total cost of ownership are needed to fully understand the system integration cost and performance benefits of SIP approaches.

The ITRS also identifies infrastructure issues that need to be addressed, including design and modeling tools; factors related to the increased requirements for cooperation among manufacturers, semiconductor suppliers, and OEMs; and functional test and built-in self test at the IC and package levels.

Conclusion

This summary has only scratched the surface of the information in the ITRS related to the future of packaging. There is much more detail in the document about packaging and the system-level issues driving packaging requirements. Information about SOC/SIP illuminates differences as well as shared challenges. Test, for example, raises similar challenges whether the component integrates multiple functions in silicon or inside of a package. Anyone who is interested in the future of packaging should take advantage of the valuable service provided by the authors of the ITRS.

Jeffrey C. Demmin is a contributing editor to Advanced Packaging magazine and on the advisory boards of Solid State Technology and Advanced Packaging. He can be reached at ph 408/383-3691 or e-mail [email protected].