Using collaboration to tame Cu/low k
03/01/2004
Solid State Technology asked industry experts how collaboration was enabling progress on Cu/low-k integration.
Low k cracks the whip
 Michael A. Fury |
Michael A. Fury, VP, R&D and engineering, DuPont EKC Technology, Hayward, California
The industry migration to copper metallization and low-k dielectrics on 300mm wafers drives a long and complex development process. A single change along the way can create insurmountable challenges — whether in terms of the time and cost constraints that drive the rapidly moving development train, or the ripple effect at the end of the chain. Consider today's fractious market in low-k dielectric films. Everyone talks about low k; everyone wants it, but so far, few can integrate it.
If low k were a single entity, like tungsten plugs in SiO2 dielectric, the industry could muster its forces and focus an all-out assault on resolving the technical barriers. But low k is a cat-o'-nine-tails, with small bands of fabs chasing each of its many threads. Each group of fabs in turn calls for integration help from its materials suppliers, help that is different for each low-k thread, stretching the suppliers perilously thin. Each crack of the low-k whip requires, at least, a compatible ARC, barrier metal, etch process, etch-stop layer, photoresist remover, etch residue remover, and CMP slurry. The chip fabs can't tell which low-k option will meet their needs until the whole integration puzzle is solved, which requires an investment by the fab.
The integration puzzle can't be solved until all of the pieces are in place, which requires an investment by each of the suppliers. At both ends of the supply chain, investment decisions are based on anticipated payback; everyone needs to improve the chances for success. Eventually, someone needs to make some money. No one wants to put all of their eggs in one basket, so options are kept open as long as tolerable. Fabs want to work with as many materials as possible, challenging suppliers with each and every alternative on the drawing board. The fact that we are still in the longest downturn in the history of our industry only makes the sting of the whip more intense. Something has got to give.
Technology is not the element that is going to give. Materials science is being stretched to the limit to satisfy all of the equations simultaneously. It's a difficult challenge, though it's arguable whether low k is inherently more difficult than roadblocks that have been overcome in the past. Where materials solutions fail us for the moment, the design world has historically found a workaround to satisfy the apparent forward momentum of technology. Once this path has been committed, the fabs are content for the short term since design solutions make use of the existing equipment and materials set, thus deferring new capital expenditure and freeing process development resources.
The business model is the element that is going to "give" this time. Past transitions from one chip generation to the next afforded to fabs the luxury of commonality in their choice of materials and process integration schemes. In turn, suppliers' markets enjoyed sufficiently large volumes so it was easy to ignore the degree of customization provided to users. In a fractious low-k development environment, however, it is no longer possible to ignore the differences between fabs, nor is it possible to ignore the brief time spent on each variation before the end user moves on, discouraged and bewildered, to the next. Since materials are being applied and processed with the standard arsenal of techniques, equipment suppliers will see much less change than their counterparts in materials will experience going forward. For the materials folks, there is a change coming — for some, it has already arrived.
The SiLKnet Alliance (www.silknetalliance.com) is an example of how suppliers can band together to develop extended segments of integrated processes and materials. Across seven process sectors, there are 17 equipment and 11 materials suppliers participating in a common, though nonexclusive, cause. All 11 materials suppliers are in the post-etch cleaning (six) and CMP (five) sectors, belying the materials intensity of these areas. Dow Chemical's carrot for the other parties is that it supplies the patterned wafers on which the others can develop their own materials and processes. In an environment where patterned wafer costs are always the rate-limiting step in the development process, this is a stroke of genius, albeit an expensive stroke. The fate of this alliance rests with the ultimate success of low-k dielectrics at their foundation; therein lies the calculated risk. But the model belies an intelligence that goes beyond any one dielectric.
In November 2002 (Solid State Technology, "Time for a Communal 300mm CMP Apps Lab," p. 88) I wrote about a communal 300mm CMP lab ("C3PO") proposed for Albany NanoTech (ANT). This concept has taken root and represents a new business model for addressing the prohibitively high cost for materials suppliers of buying, installing, and operating capital equipment. A 300mm CMP facility was part of the original master plan for ANT. Additional process and metrology equipment has been added to bring the facility from a university research level up to industrial expectations for process development. Slurry and pad suppliers will be able to purchase blocks of time in the facility to develop 300mm processes without making the capital commitment up front, if ever. The customers benefit from consumables pricing unburdened by capital depreciation. Operating expenses are generated on a pay-as-you-go basis. Further announcements about this facility are planned for later this year.
For materials suppliers, the old ways of doing business are not going to serve us very well in the age of copper interconnects and low-k dielectrics. While "the decade of materials" takes hold in the semiconductor industry, process integration is still king — levying the taxes and cracking the whip. Anyone who doesn't give some serious thought to how the business model has to evolve is in for a rough ride. Creative, cost-effective alliances among parties with common goals seem more likely than ever to become the ideal prime minister to serve this demanding king.
For more information, contact Michael A. Fury at DuPont EKC Technology, ph 510/780-1340, e-mail [email protected].
End-to-end collaboration: Meeting low k head-on
 Wilbert van den Hoek |
Wilbert van den Hoek, CTO and executive VP, integration and advanced development and CMP Business Group, Novellus Systems Inc., San Jose, California
The biggest challenge facing the semiconductor industry these days is the successful integration of low-k dielectric films with a k<3. As a whole, the industry failed at the 130nm node, but has been more successful at the 90nm node.
Interestingly, the difficulty in implementing low-k films has not been a traditional unit process-technology issue. The industry has been able to deposit dielectric films with k values <3 for a number of years, using either chemical vapor deposition (CVD) or spin-on technologies. Instead, the challenge has been in understanding the full range of integration issues involved in successfully building interconnect stacks with these films. For the semiconductor equipment industry, this means expanding our expertise beyond the unit process issues with which we have traditionally been concerned. We need to start looking at semiconductor manufacturing as a series of increasingly interdependent process steps that need to be successfully integrated into superior unit processes.
If the supply chain is going to help IC manufacturers overcome the challenges posed by low-k integration in future generations, then it not only has to be able to build interconnect structures, it has to be able to test them to identify, analyze, and then resolve potential problems. Additionally, since many of the low-k failures occur during packaging, an understanding of how that process affects these films is also needed. Considering the cracking and delamination problems experienced at 130nm, it's clear that device packaging is key to successful low-k integration.
To deal with these challenges, Novellus is currently expanding the scope of its Damascus Alliance — originally focused on exploring the interactions between the different unit processes required to build copper interconnects. The alliance was developed as an open association of process-technology vendors who worked together in a collaborative, pre-competitive learning environment to resolve key process integration issues before selling new unit technologies. Alliance members benefit from this process of sharing costs and expertise through the ability to fine-tune their processes in the manufacturing environment provided by Novellus' Customer Integration Center. Today, the alliance is looking beyond issues such as resist poisoning, via stress migration and electromigration, and is coming to understand process integration issues that often don't arise until the backend.
This more comprehensive approach — which considers the effects of all stages in the semiconductor manufacturing process on the device, rather than just those required to build the interconnect — has led the alliance to expand into the areas of detailed electrical test and failure analysis to understand the root causes of reliability failures. The recent addition of Keithley to the group, for example, has enabled detailed parametric and long-term reliability testing, while the addition of FEI has added failure analysis to the alliance's toolbox. These expanded capabilities are helping users to determine which integration problems might have led to a degradation in device performance that may have caused the failure of just a couple of vias out of possible millions on a device.
Since packaging has been recognized as a critical area, the alliance is also using a commercially available semiconductor-packaging company to package test die for complete characterization. The next step will be to expand efforts by establishing close collaboration with leading-edge packaging manufacturers for a better understanding of the interactions between mechanically weak low-k films and the packaging process.
With the shift in focus from copper implementation to low-k integration, a comprehensive approach that integrates collaborative efforts will be key to solving the sophisticated challenges posed by low-k implementation.
For more information, contact Wilbert van den Hoek at Novellus Systems Inc., e-mail [email protected].