Microfabrication process enables 3D metal microdevices
03/01/2004
Overcoming the limitations of MEMS technology based on planar silicon techniques can be achieved by sequential deposition of high-conductivity metals. This approach enables the design of different structures, including high-Q RF devices, on the same substrate without the need for manual processing.
By Chris Bang, Richard Chen and Dan Feinberg
Broad-based commercialization of microdevices requires an alternative approach to overcome some of the barriers related to silicon-based microfabrication technologies. A batch process has been developed — from the ground up — to address this need and promises to expand the use of micromachining in many new application areas that require 3D metal-based microdevices.
The technology — called EFAB — is an additive microfabrication process based on the selective electro-deposition of multiple patterned layers of materials such as nickel, silver, copper, gold, or any other metal that can be electro-deposited. The process can create devices with arbitrary geometries from 3D CAD data, and is better suited to addressing applications that demand higher performance levels in terms of functionality and materials.
For instance, in high-frequency applications where the advantages of high-conductivity metals have been clearly identified, metal-based microfabrication processes that support metallic 3D structures are required. Good examples are RF passive devices, where metal-based devices can provide very high Qs compared to their IC counterparts. Due to the inherent 3D nature of the new technology, the device and package can be concurrently designed and fabricated with the potential to solve difficult packaging problems that have plagued the silicon-based MEMS industry. Because it is a metal-based, room-temperature process, it offers the potential for generic IC integration without the need for additional space on an IC wafer.
Prior to the new microfabrication technique, MEMS designers had been forced to make severe compromises during the design phase to conform to the limitations of a process that is inherently planar. Optimal performance usually cannot be achieved with planar MEMS. In fact, the limitations of microfabrication are so ingrained into the conventional MEMS design methodology that even microfabrication textbooks identify boundaries and limitations for MEMS devices that are based not on physics, but on assumed process limitations.
Three-dimensional design opens up new application areas and solves problems that have hampered the MEMS industry. Using the new process, high-conductivity metals can replace silicon, and complex geometries, such as coil inductors and mechanical springs, can be automatically generated without manual processing. Since geometry is no longer specific to a given process flow, one can design different or even unrelated devices on the same substrate, making complex systems and mechanisms possible.
In addition to 3D design, the process provides benefits to the microdevice product-development process and manufacturing. Devices can be prototyped much more quickly than conventional MEMS devices, reducing product development time and allowing faster design iterations and optimization.
Process description
Metal structures are created by electroplating multiple independently patterned layers. The process is similar in concept to rapid prototyping techniques such as stereolithography in that multiple patterned layers are stacked to build structures with virtually any desired geometry. Unlike stereolithography, it is a batch process suitable for volume production of fully functional devices, not just models and prototypes. Also, it provides engineering materials (metals rather than polymers) and far greater precision than stereolithography.
Each layer made with the new technique contains patterned structural and sacrificial materials that are planarized, allowing each layer to be deposited over the previous one without geometric constraint. The layer's structural material can overhang or even be disconnected from the previous layer's. Such geometric freedom realizes monolithically fabricated "assemblies" of discrete, interconnected parts, eliminating subsequent bonding or assembly steps, and allowing device fabrication of up to 12 completed layers/day. In contrast, it can take 8–12 weeks to complete the fabrication cycle of silicon-based microdevices needing as few as 7 photolithography steps.
Devices can be designed in any conventional 3D CAD package. Layerize software translates the finished CAD file into a series of 2D slices that contain a cross-section for each layer. A mask set is then generated that includes all the unique cross-sections of the device. The CAD designer is able to create structures in a what-you-see-is-what-you-get fashion, without having to perform any process flow design. The design and fabrication are decoupled, making microfabrication accessible to designers without experience in semiconductor process technology.
 Figure 1. The EFAB process. |
The EFAB process consists of the following primary steps, repeated on every layer (see Fig. 1): 1) selectively depositing a first material; 2) blanket depositing a second material; and 3) planarizing.
In the first step (Fig. 1a), a layer is patterned as deposited. A second blanket deposition (1b) fills the spaces left in 1a. The topography is fully planarized in 1c, resulting in a flat surface suitable for the next patterned deposition. The process cycle (a through c) is repeated until the full desired height of the device is achieved (1d). Finally, after the build is completed, the substrate is placed in a release etchant that removes the sacrificial material, leaving behind the freestanding device (1e).
Layers from 2–20µm in thickness and in any combination can be formed with multiple layers to fabricate substantially larger and more robust devices than possible with conventional planar micromachined devices, which are usually formed from thin-film materials just a few microns thick. This is particularly important in actuator applications for generating higher forces.
The process also can be used to form structures from any metal or alloy capable of being electro-deposited, with the only constraint being that the accompanying sacrificial metal must be selectively etched after the layers are formed. Devices can also be fabricated on a variety of substrates, including dielectrics, to form electrically isolated devices. The process currently accommodates 4-in. substrates, and will be upgraded to 6 in. in late 2004. Figure 2 shows an example of the variety of 3D structures that can be fabricated on a single substrate in the same fabrication run.
Application examples
The ability to generate 3D devices with essentially no limitation on the number of layers addresses a broad range of applications and design requirements, and provides designers with flexibility to produce devices previously impossible with more conventional silicon-based micromachining processes. The following application examples illustrate some devices that can be generated from 3D CAD models.
The most commonly used actuators in micromachining are based on electrostatic attraction. The two main types of electrostatic actuators are comb-drive and gap-closing actuators. Comb-drive actuators have alternating interdigitated comb fingers that move parallel with each other when a potential is applied. Gap-closing actuators are based on parallel plates that are drawn toward each other when a potential is applied across the plates. Electrostatic actuators are popular because of their relative ease of fabrication and virtually zero power consumption. Unfortunately, high voltages are usually applied to generate significant forces. The force is maximized by minimizing the separation between the electrodes and increasing the area of the capacitor plates.
Using the new process, large-force comb-drive actuators can be designed by increasing the height of the comb fingers. The force of gap-closing actuators can be significantly increased by increasing the actuator height for lateral actuators or by increasing the number of capacitor plates for vertical actuators.
Achieving good inductor performance for RF applications has required space-consuming off-chip components. Integrated planar inductors, resting on the semiconductor substrate, have inherently large losses to the substrate, and consequently low Q values. With the new technique, it is possible to create high-Q inductors utilizing high-conductivity metals and virtually any 3D geometry. Dimensions can be selected to optimize Q and inductance at the required frequency, while elevating the inductors above the substrate to reduce losses. Because all process steps are low temperature, it is possible to fabricate inductors directly on IC circuitry for improved performance and reliability, at reduced space and cost. Inductors may also be integrated with dielectric (e.g., ceramic or glass) substrates. Figure 3 shows two types of 3D inductors fabricated with the new process.
 Figure 3. Examples of inductors produced using the new process. |
Variable capacitors are critical frequency tuning components for a wide range of RF applications. Integrated reverse-biased p-n junction capacitors, resting on the semiconductor substrate, have inherently large losses to the substrate, and consequently low Q values. It is possible to optimize Q as well as nominal capacitances and capacitance tuning ranges utilizing high-conductivity metals and 3D geometries, such as stacked parallel-plates and high-aspect ratio comb-fingers, by using the new manufacturing technology. The process-layer thicknesses allow designers to optimize actuation voltages and speeds to meet the typical design requirements for RF variable capacitors.
 Figure 4. Cutaway view of Ka-band bandpass filter produced with the EFAB process. |
Current fabrication processes for transmission coaxial filters that operate at frequencies >10GHz are very expensive and usually cannot take advantage of batch processing. Using the new process, however, a Ka-band bandpass filter has been developed with a distributed design based on a three-pole Butterworth design and two impedance-inverting sections. The filter layout accommodates sharp turns to fit into a small footprint of approximately 7 × 7mm, with the center conductor, supported only at the ends of the stubs, otherwise floating in air. Device fabrication required 40 layers. SEM photos of the entire device and at metal layer 25 are shown in Fig. 4.
Conclusion
Success in microdevice applications will depend more on understanding a variety of fabrication approaches and using the right fabrication technology or combination for a given set of requirements. A variety of new application areas, particularly in high-frequency applications that have not been well served by existing microfabrication technologies, will be enabled by 3D metal microdevices fabricated with EFAB technology.
Acknowledgments
EFAB and Layerize are registered trademarks of Microfabrica Inc.
Chris Bang is VP for design and applications at Microfabrica Inc.
Richard Chen is senior MEMS designer at Microfabrica Inc.
Dan Feinberg is director of sales and marketing at Microfabrica Inc., 1103 West Isabel St., Burbank, CA 91506-1405; ph 818/295-3996 ext 125, fax 818/295-3998, e-mail [email protected]; or for more information, go to www.Microfabrica.com.