High-performance SiGe pHMOS using reduced-pressure CVD
03/01/2004
A high-performance SiGe p-type metal-oxide-semiconductor heterostructure field effect transistor (pMOS-HFET or pHMOS) has been developed using a well-controlled boron delta-doping and SiGe/Si heterostructure epitaxial process with reduced-pressure chemical vapor deposition. Along with high-speed operation and excellent 1/f performance comparable to bipolar junction transistors, practical issues like power consumption and thermal dissipation will drive SiGe pHMOS technology into gigabit-scale integration in the sub-decanano generation.
By Kyu-Hwan Shim, Young-Joo Song and Jin-Young Kang
As semiconductor technology evolves into the sub-100nm era, Si MOSFET devices span applications from conventional digital and analog ICs, to high-performance applications [1–2]. According to projections of the International Technology Roadmap for Semiconductors, the supply voltage in the 45nm generation is expected to scale down to 0.6V, and the major RF parameter, ft, is expected to get up to 175GHz. By 2010, silicon-based ICs will become communication components at a few tens of gigabit scale while operable at high data transfer rates, e.g., optical transceivers at 80Gbit/sec and various wireless ICs from RF to millimeter waves at >400Mbit/sec.
However, several critical issues need to be resolved to achieve such progress. Reliable process technologies must be able to manipulate device structures in nanoscale dimensions with sufficient reliability and repeatability. Second, and even more basic, a novel transistor consuming little power is essential to avoid thermally induced failures due to heat dissipation in dense ICs. Another issue will be the short channel effect (SCE), which is the usual origin of serious difficulties associated with nonlinear properties in signal transfer.
The last critical issue for Si MOS devices is the large noise level at low frequency (LF), called 1/f noise to denote its characteristic frequency dependency [3–6]. Regardless of extensive efforts, the 1/f noise characteristic of Si MOS is worse than for other competing microelectronic devices, and it becomes more serious at gate lengths of 50nm, since the corner frequency, fc, increases in value up to 110MHz. The inherent nature of the MOS structure with its unavoidable incorporation of charge traps in gate oxides is one of the crucial obstacles prohibiting Si MOS transistors from being extensively used in high-performance ICs.
SiGe HMOS, however, can get rid of many of the above difficulties. Electrons and holes confined in a strained-Si (or -SiGe) channel may move faster by 3–8× compared to Si-control devices, and the power consumption decreases in a similar manner. More importantly, the 1/f noise can be suppressed by reducing both carrier trapping rates and scattering efficiency. But only a few research groups in the world have devoted time to this issue and there are many unknowns that remain to be uncovered.
SiGe/Si heterostructures have mostly been grown by molecular beam epitaxy (MBE) and ultrahigh vacuum chemical vapor deposition (CVD). Reduced-pressure chemical beam deposition (RPCVD) has only rarely been used to investigate the SiGe/Si heterostructure due to the presumed difficulties in achieving a sharp and controlled delta-doping technique. A frequently mentioned hurdle is the detrimental germanium-oxides formed at interfaces of gate oxide and channel by Ge atoms that pile up under high temperature. Recent works, however, explain that such pessimistic speculations can be resolved [7]. In this work, in which CMOS compatibility has been emphasized, the SiGe pHMOS was developed by RPCVD through an in situ modulation doping process at different doping levels. Investigations were performed to evaluate both the DC and AC characteristics of SiGe pHMOS, which were observed to be superior to those of Si pMOS. In particular, special attention was focused on the 1/f performance in conjunction with device parameters and potential future uses.
Fabrication processes
As Si CMOS technology is scaled down to deep submicron dimensions, a higher transconductance in p-channel devices is essential for improving the packing density and operating speed of ICs. Recently, use of a SiGe strained quantum-well (QW) channel has received attention because of its rapid transit speed of carriers. In SiGe pHMOS, a thin Si-cap layer (<10nm) is normally employed to use high- quality thermal gate oxide by preventing oxidation and segregation of germanium atoms. A Si-cap layer, however, tends to form a parallel channel at the SiO2/Si interface, and lowers hole mobility. A widely used technique to compensate for this effect is a 2D modulation doping of dopants below and/or above the channel to supply more carriers into the channel.
At first, twin-tub and LOCOS isolation were formed on Si wafers. After opening the active area of the n-well, the SiGe/Si (XGe = 0.2) heterostructure was grown on the wafers by RPCVD. The SiGe/Si growth started with a 50Å Si seed layer followed by a 2D boron doping. The in situ 2D boron doping technique was developed for doping concentrations of 3×1017 ~8×1019 cm-3. Then, a 10nm-thick Si spacer, a 20nm Si0.8Ge0.2 channel, and a 7nm Si capping layer were grown. A low-temperature oxidation <800°C was performed in a H2/O2 ambient for a 7nm-thick gate oxide. The oxide-semiconductor interface state density (Dit) was controlled at 4.4×1010 cm-2eV-1, which is almost the same as the 4.2×1010 cm-2eV-1 value used in the Si-control device. No sign of strain relaxation was observed after the oxidation.
Finally, all the wafers were switched back to the regular CMOS process, and then fabricated up to the second metallization. Shown in Fig. 1 is the scanning electron micrographic (SEM) image of a multifinger SiGe pHMOS developed in this work. The active area was isolated using the first interconnection metal to minimize any possible noise transfer from surroundings.
DC & AC characteristics
Data in Fig. 2 was measured in the Si-control device and in the SiGe HMOS device and shows the characteristic current-voltage curves of MOS gates. The overall current curves — including the Fowler-Nordheim (F-N) tunneling regime (see inset) — were measured and found to be consistent. The breakdown electric fields are obtained as high as ~12MV/cm. Almost identical current-voltage curves indicate that the SiGe channel does not introduce any considerable leakage path during the thermal cycle for gate-oxide formation. The possible formation of defects associated with germanium-oxide formation looks negligible, otherwise their chemical instability could devastate gate-oxides.
The current-voltage characteristics plotted in Fig. 3 represent typical advantages of SiGe HMOS with features of increased channel conductance and suppressed SCE; their DC and AC properties are summarized in the table. The transconductance measured at VDS = -3V and Vgs -Vth = 2.5V was increased by 9% in SiGe pHMOS compared to the Si-control, 76.7mS/mm and 83.3mS/mm, respectively. SCE was greatly improved in SiGe pHMOS by a 30% decrease of DIBL, measured from 12.4–8.7mV/V. The pHMOS also exhibits a reasonable Ion/Ioff ratio>2.73×108, as does the value of 2.55×108 for the Si control.
A greater number of carriers in the SiGe channel, supplied from the modulation-doped layer, seem to suppress the parallel channel effect. From prior experiments, it was observed that the modulation doping level should not exceed a certain value for the best device performance [7]. For instance, the SiGe pHMOS with a 3×1018 cm-3 modulation doping leads to maximum values of 34% and 51% of the Gm-max and IDS improvements, respectively, compared to the Si-control device. Meanwhile, the threshold voltage of SiGe pHMOS is slightly more positive than that of the Si-control: Vth values are -0.87V for the 3×1018cm-3 doped HMOS and -1.04V undoped, compared to -1.12V for the Si-control. The smaller |Vth| value of the SiGe pHMOS structure had been expected because holes are mainly located in the QW channel at a lower |Vgs|, resulting in the quicker turn-on of the QW channel than the surface.
Low-frequency noise properties
The low-frequency noise behavior of submicron Si MOS is driven by high-speed applications, in which minimal noise is a critical issue. The dynamic range and sensitivity of a wireless transceiver are affected primarily by the noise figure of a low-noise amplifier, and selectivity is determined by the local oscillator phase noise. Development of a low flicker noise device is crucial for applications in digital and analog circuits at frequencies up to about 10–30GHz, with reduced jitter and phase noise, respectively. This is important because small improvements in device properties have a large impact on system performance.
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Despite the many analyses discussed in the literature, the origin and behavior of noise in MOSFET devices are not yet clear, and most of the understanding is based on empirical relations. Yet it can be said that noise in MOS devices consists of three characteristics. The device noise at low frequency follows a 1/fγ (γ = 0.8 ~ 1.2) dependence called flicker noise or 1/f noise; above a corner frequency, fc, the device noise is frequency-independent due to thermal and shot noise; at high frequency, the device noise increases due to parasitic resistance and capacitance coupling [3].
LF noise is characterized by a power spectral density in A2/Hz for the current noise:
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where Kf is a flicker noise coefficient, and α and γ are exponents defining the drain current and frequency dependence. The origin of Lorentzian spectrum relies on the thermally activated capture and emission of charge carriers by trap or generation-recombination center. Since the Lorentzian noise spectrum corresponds to a random telegraph signal (RTS) in small-area MOSFETs, it is strongly believed that RTS is one of the fundamental components of 1/f noise.
Basically, a low flicker noise level is usually attained in silicon bipolar junction transistors (BJT), because the carriers transit in bulk, not exposed to the oxide-silicon interfaces. Most oscillators are made of BJTs because of their lower flicker noise levels — as low as 10~30dB below that of conventional MOSFETs.
Conversely, MOS flicker noise is caused by carrier trapping-detrapping at the gate-oxide channel interface. Gate-oxide traps and interface defects existing 1.5nm apart in the channel are detrimental, and the density of mid-1010eV-1cm-2 at the Fermi energy level also contributes. As MOS technology enters into the sub-100nm era, the cutoff frequency and high-frequency noise, which approach 100GHz and 0.1dB, respectively, raise the performance of ICs and, thus, communications systems. However, the flicker noise exhibits a substantial increase in Si MOS made of shorter gates utilizing gate oxides as thin as ~2nm, limited by the gate leakage problem. Flicker noise in nMOS is increased by 30dB as the gate length becomes shorter, i.e., from 0.5µm down to 50nm. Thus, for the practical future application of nano-CMOS, it is crucial to lower flicker noise level by two orders of magnitude or even more. Scaling of Kf, α, and γ with decreasing gate length needs to be accounted for quantitatively, and this scaling at sub-100nm technology nodes is the subject of work in progress.
 Figure 4. Normalized power spectral densities measured at VDS = 100±5mV and Vg = Vth - 0.7V as a function of frequency for Si-control MOS and SiGe HMOS devices. |
The drain-current noise power spectral density (PSD), normalized by the drain current as ID2 as plotted in Fig. 4, was measured as a function of frequency for Si-control and SiGe HMOS. The noise PSD measured lower by two orders of magnitude in SiGe pHMOS compared to the Si-control device. At the same time, the corner frequency of 7KHz for the pHMOS structure was much less than that of the Si-control, ~1MHz corresponding to the prevalent values of conventional CMOS devices. Our experimental results demonstrate that the Si-cap thickness in the range of 2~5nm is acceptable in terms of low noise PSD, although a thinner Si-cap is favored considering DC characteristics [8]. A two orders-of-magnitude decrease in flicker noise implies that the 1/f noise in SiGe HMOS could be controlled to be as low as that of BJT structures.
Fowler-Nordheim stress
It is important to figure out whether sound interfaces could be maintained in SiGe/Si/oxide heterostructures. Data points in Fig. 5 are the drain current noise power spectral densities measured at 30Hz for Si-control MOS and SiGe pHMOS devices. For F-N stress, the current flow was equally controlled while a negative bias of -10V was applied between the gate and the source and drain electrodes. The data at a Si-cap thickness = 0 are obtained from a Si-control device instead of from a pHMOS structure without a Si-cap. The pHMOS structure without a Si-cap layer results in even worse 1/f noise properties.
It is clear that SiGe pHMOS devices have significantly lower 1/f noise levels than the Si-control devices by an order of ~2 even after F-N stressing, regardless of how the noise level was elevated by the stress for both samples. The 1/f noise of pHMOS devices has been proven to be maintained at a low enough level even after the gate-oxide is damaged by the F-N stress. The reliability of devices, including life-time, directly depends upon the F-N stress-induced leakage current and 1/f noise properties. The behaviors described above clarify that the SiGe/Si heterostructures, if properly tailored, should improve the reliability of MOS devices.
As conventional Si MOS technology enters into the nanoscale generation, the 1/f noise problem — which had been a detrimental hurdle to the practical use of high-speed ICs — could be lessened by using SiGe pHMOS technology, which lowers the 1/f noise level to as low as that found in silicon BJTs. Intel announced that its 52Mbit SRAM embedded Pentium processor with strained-Si MOS is in volume production, with a 20GHz microprocessor planned by 2007. Additionally, IBM has announced that its 65nm SiGe HMOS would be in mass production in early 2005. Since ETRI started SiGe research in 1992, many journal papers have been published and more than 100 patents have been filed in several countries, including the US and Japan.
Conclusion
High-performance SiGe pHMOS transistors have been developed using well-controlled boron delta-doping and SiGe/Si heterostructure epitaxy via reduced-pressure CVD processing. Compared with Si-control devices, SiGe pHMOS devices displayed enhanced transconductance up to 83.3mS/mm and had an improvement of 9%. The pHMOS structure also exhibits a reasonable threshold voltage of -0.96V and a high Ion/Ioff ratio > 2.55×108, and the process is potentially suitable for high-density and high-speed CMOS applications.
The pHMOS device attained extremely small 1/f noise levels by a factor of 1/100 compared to the Si-control device. The minimum parallel channel effect and the lower density of interface states are responsible for the remarkable decrease in noise power spectral density, 1/f noise, and the prohibition of catastrophic degradation of 1/f noise after F-N stress. Along with highly improved reliability, pHMOS devices are suitable for applications requiring a low 1/f noise like voltage-controlled oscillators and gigahertz digital ICs. Moreover, pHMOS structures may become more useful in the sub-decanano technology era with extremely small jitter and phase noise levels.
Acknowledgments
The authors would like to acknowledge the contributions of co-authors J.H. Kim and J.I. Song from KJIST; K.W. Park from the U. of Seoul, and J.W. Lim from the Information Display Team in ETRI. The National Research Laboratory Program is supporting this work under Grant No. MI-0302-00-0050 of KISTEP organized by the Ministry of Science and Technology of Korea.
References
- D.Y. Lie, K.L. Wang, Handbook of Advanced Electronic and Photonic Materials and Devices, Academic Press, 2002.
- M. Bulsara, Compound Semiconductor, pp. 39–43, Sept. 2002.
- S. Martin, V.D. Archer III, D.M. Boulin, M.R. Frei, K.K. Ng, et al., Bell Labs Technical Journal, pp. 30–45, Summer 1997.
- G. Ghibaudo, Microelectronic Engineering, Vol. 39, pp. 31–57, 1997.
- E. Simoen, C. Claeys, Materials Science and Eng., Vol. B91, pp. 136–143, 2002.
- Z. Celik-Butler, IEEE Proc.-Circuits Devices Syst., Vol. 149, pp. 23–31, 2002.
- Y.J. Song, J.W. Lim, J.Y. Kang, and K.H. Shim, IEEE Electronics Lett. 38, pp. 1479–1480, 2002.
- Y.J. Song, J.W. Lim, B. Mheen, S.H. Kim, H.C. Bae, et al., IEEE Trans. on Electron Devices, Vol. 50, pp. 1152–1156, 2002.
Kyu-Hwan Shim is a principal research member on the SiGe Device Team at the Electronics and Telecommunications Research Institute (ETRI), 161 Kajeong-Dong, Yuseong-Gu, Daejeon 305-350 Korea; ph 82/42-860-4927, fax 82/42-860-6183, e-mail [email protected].
Young-Joo Song is a senior research member of the SiGe Device Team.
Jin-Young Kang is the director of the SiGe Device Team.