Technology News
02/01/2004
Intel makes 0.57µm² SRAM cell using 65nm logic
Fully functional 4Mbit SRAM arrays have been fabricated using 65nm logic technology — with all bits working — in a 0.57µm² cell containing six transistors by Intel Corp (Fig. 1). The announcement comes 20 months after Intel released data on a 1.0µm² cell using its 90nm process.
 Figure 1. SEM of 0.57µm2 six-transistor SRAM cell. (Source: Intel) |
Intel Senior Fellow Mark Bohr said that the company is on target to put its 65nm process into production of microprocessors in 2005 at the company's D1D 300mm fab in Hillsboro, OR. Intel also plans to develop and manufacture its 45nm logic technologies at D1D. There was no comment on whether or not Intel will offer two versions of its 65nm process — one for logic and one for communications.
In keeping with the company's previously stated strategy of re-using about 70% of its process tools when going from one technology node to the next, Bohr said the same strategy will be used in going from 90nm to 65nm production. A mix of 193nm (dry) and 245nm lithography tools were used for the 65nm SRAM development, although Bohr indicated the company would be buying some upgraded 193nm (dry) lithography tools for 65nm production. He declined to identify what tools or techniques were used for the SRAM development, although he did say the company is considering immersion 193nm tools as an option below 65nm.
Bohr attributed the progress at 65nm in part to the company's ability to control the lithographic process, as well as controlling defects. While the industry is seeing exploding mask costs in going from one technology node to the next — particularly at 90nm and beyond — Bohr said that the cost of masks is a small part of the production cost/chip for Intel and that there is no cheaper way of doing things — OPC and APSMs will add to cost.
Explaining the significance of the noise margin performance attained to date, Bohr stated, "SRAMs don't operate in a perfect world and 'high' and 'low' signal levels aren't always as intended. Slight imperfections in transistors or electrical noise introduced by adjacent circuits can cause voltage levels to vary and a 'high' signal level may be lower than expected, or a 'low' signal level may be higher than expected."
 Figure 2. SRAM noise margin. (Source: Intel) |
Interpreting the noise margin data (Fig. 2) released with the announcement, Bohr noted that at an operating voltage of 1.1V, "The 'low' signal level can increase to ~0.45V and the 'high' signal level can decrease to ~0.80V before the cell will start to indicate the wrong binary '1' or '0' state. This noise margin decreases with the use of lower operating voltage (i.e., at 0.9V and 0.7V, the noise margin "boxes" are smaller)."
In other developments, Bohr confirmed that Intel used alternating phase shift masks (APSM) to do the work at 65nm, although he would not confirm that APSMs are being used for the company's 90nm process. Strained silicon was also used at 65nm (the company started using strained silicon at the 90nm node). Bohr noted that the company has no plans to use SOI at the 65nm node because it sees no significant performance advantage. The company's recent high-k discovery came too late for incorporation into the 65nm generation, but Bohr added that very likely, it would be used at 45nm. He also noted that the tri-gate transistor structure is sill one of several options being considered for the 45nm node. Bohr also declined to identify the supplier of the low-k process or equipment used for the 65nm SRAM development.
The research team is still in the early phases of reliability evaluation of the design. —D.V.
Structured ASICs may lower mask costs
By combining preprocessed wafers from TSMC — up to metal level 2 — and then providing custom programming for as many as five metal levels, AMI Semiconductor says it can cut the cost of reticles to about one-quarter of the usual cost. "We make the initial investment once and customers don't have to pay over and over for a complete mask set, as they would with a cell-based design," explains Vince Hopkin, company VP of digital ASICs.
In the structured ASIC process, libraries are used to build the device, just as in cell-based ASICs, except pad counts and the number of gates and amount of memory are set — but able to be selected as desired through programming. In contrast, cell-based ASICs are built from the ground up, using standard library elements in an array-based architecture; the elements are not programmed. Having the pre-processed base stock wafers that are purchased in quantity from TSMC, combined with a set-up that fits small volume production runs, provides flexibility, according to Hopkin.
Admittedly, cell-based ASICs are still a good deal for companies with high-density (e.g., >5–10 million gates or 10–40 million transistors), high-volume products. Hopkin says,however, that cost savings afforded by structured ASICs are helping companies that have high performance, medium density ≤5 million gates, or ≤20 million transistors) products that need fast time-to-market. For medium density and below products, FPGAs also work and the NRE costs associated with them are low at the front end, but FPGAs are expensive to manufacture on a per unit basis, says Hopkin.
Suppliers reduce costs of blanket epitaxial strained silicon
Suppliers of strained silicon say they're not seeing any letup in interest in evaluations of their blanket epitaxial products, despite the fact that none of the first announced strained silicon applications have actually used the costly new wafers, but have instead just engineered the strain in locally by a few extra process steps. New technologies that appear likely to bring down costs significantly should help make the blanket strained silicon wafers more appealing. But some clear industry standards would also help suppliers focus development efforts on the right specifications.
Amberwave Systems Corp., Salem, NH, says it should be able to bring the cost of a 200mm strained silicon wafer down to $750 in volume production this year, down from around $1500 currently. Key to the improvement is using GeCl4 for the source, which allows a higher processing temperature and thus a growth rate that's four times faster, using the same standard epi tools from ASM or Applied Materials. Other currently used source materials tend to coat the chamber and produce particulates that flake off, damaging quality and requiring frequent cleaning, unless the growth is done at lower, slower temperatures. GeCl4 is commonly used as a source for optical fiber preforms, so it is readily available. CTO and cofounder Mayank Bulsara says 200mm strained silicon wafers could eventually get down to less than $200 in high-volume production. The company has been giving presentations in Japan talking about lowering prices to $400/wafer by next year, close to that of SOI wafers.
UMC has reported 25–30% improvement in NMOS current, 5–10% improvement in PMOS, in a 70nm MOSFET using an Amberwave strained silicon wafer. Amberwave has licensed its proprietary CMP process to wafer maker SUMCO.
Meanwhile, IQE Silicon Compounds is bringing down its production costs with a different deposition process that allows it to skip the intermediate CMP step usually needed to smooth the first SiGe layer before deposition of the top SiGe and the strained silicon. The company says it optimizes the deposition kinetics to keep surface micro-roughness levels low enough to do the whole process in a single stage This eliminates not only the cost of the CMP process, but also the related processes of wafer cleaning before regrowth, loading and unloading, and growing excess expensive SiGe just to remove it by polishing. Technical sales manager Robert Harper says volume production costs for bulk strained silicon with 17% SiGe should be in the same ballpark as bonded SOI wafers. And since epitaxial growth times for 300mm wafers are about the same as for 200mm wafers, the larger wafers should cost about the same.
"Many other options aren't so reasonable in cost," says Bulsara, noting that moving to strained silicon could extend the life of current production equipment. "People are used to looking at silicon as not value-added. But they can invest hundreds of millions in other technology — or just pay a little extra for the wafer."
Suppliers note, however, that they could get better blanket strained silicon out faster if they could get more specifics from all those users with development programs on just exactly what it is they need. "I was at a SEMI workshop meeting earlier this year and it was stated that strained silicon would have to be ready when needed — this is a tall order since nobody is defining the specifications," says Harper. "A standardization process involving IDMs, wafer suppliers, and tool vendors would be a big step forward and ensure that the appropriate materials were available when needed." He notes, however, that IQE is now starting to get more interaction with some of its development partners in leading-edge sub 100nm fabs to get more feedback on electrical and yield data that help it see if it's focusing on the materials characteristics that matter the most.
Suppliers say their blanket strained silicon wafers are now being tested in the research labs of the big chipmakers, driven by the fact that high-k transistors don't appear to work much better than those with conventional gate oxides without strained silicon to improve effective mobilities. Bulsara figures it will take another 12–18 months to establish the manufacturing processes, so he expects to see prototypes in 2005–2006. Harper expects to see some first devices on blanket epi wafers this year, with some level of volume production shortly thereafter.
Though the strained silicon wafer suppliers have no special insights into the detailed specifications of the locally engineered strained silicon reported by Intel, Texas Instruments, and Japan's Mirai project, they wonder how its manufacturability compares to the very robust and repeatable strain levels produced by the blanket approach. "I'd be surprised if the consistency of the strain levels resulting from the process induced strain techniques were as good," says Harper.
Development of basic manufacturing process technology also helps bring down the cost of blanket epitaxy strained silicon. While development wafers have used thick layers to allow lots of margin for error and best possible quality, improving technologies and better process control is allowing much thinner layers, which improves throughput. Progress on developing metrology tools specifically for strained silicon also is helping to improve quality control. Amberwave is working with ADE and KLA-Tencor to establish specific strained silicon recipes for standard tools. — Paula Doe, news correspondent
ASML demos immersion lithography
This SEM image from an ASML TwinScan scanner shows 90nm lines that were printed through focus using immersion optics on an ASML TwinScan scanner platform. ASML modified a 0.75NA 193nm dry lens to provide full-field immersion imaging, with the scanner moving at full speed across the full 26 × 33mm field of the modified lens. Depth of field doubled for this lens, and a binary mask was used. ASML demonstrated its work on immersion lithography at an analyst's conference in Veldhoven, The Netherlands. (Photo courtesy: ASML)
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