Issue



Conference Report IEDM '03: Production-ready solutions and way-out ideas


02/01/2004







Washington, DC, buzzed with clever process tricks, novel device structures, and some potential disruptive technologies for the future at the IEEE's International Electron Device Meeting, held Dec. 8–10. Highlights included:

  • intensive work on solving problems and improving performance of thin hafnium-based high-k dielectrics,
  • new approaches to creating strained silicon to speed CMOS circuits,
  • progress on workable low-k dielectric schemes for sub-100nm nodes,
  • new types of dense memory devices, including promising work on nonvolatile phase-change memories,
  • a self-limited laser thermal process (LTP) for ultrashallow junction formation for 50nm-gate CMOS devices, and
  • futuristic work on nanotechnology and techniques for creating novel devices on nanowires using chemicals.

As usual, there were revelations about devices just going into production, wide-ranging discussion of problems and potential solutions for the next few nodes, some novel device concepts, and stimulating discussion of R&D on completely new types of future device technology, such as plastic transistors on flexible substrates and on wearable fibers.

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Several problems concern developers of Hf-based high-k dielectrics for gate stacks and memory cells, including diffusion into the channel region, thermal stability, and threshold voltage drift. Stanford U.'s J.R. Jameson suggested that there could be a serious device-integration problem with dielectric oxides using materials such as hafnium or zirconium because of a residual polarization after a voltage is removed. The effect, called dielectric relaxation (DR) — first cited in a paper by Reisinger, et al. two years ago at IEDM — causes logarithmic shifts in VT over time that can't be processed away, Jameson suggested. The DR effect is several orders of magnitude higher for the high-k dielectric materials than today's SiO2. A new theory developed by the Stanford group suggests it is due to tunneling through double-well potentials in amorphous materials, and the VT drift has a complicated dependency on the entire bias history of the dielectric. Jameson suggested the crystal could not be made perfect enough to avoid the effect, which can even occur at grain boundaries.

This presentation was followed by an exchange with an IMEC researcher who said his group had put in an interface layer and the effect had gone away. Jameson replied that since it is a bulk effect, he was surprised at these results.

A HfN/HfO2 gate stack proved to be thermally stable with excellent leakage, low boron penetration, and an equivalent oxide thickness (EOT) of <10nm, according to a group from the Institute of Microelectronics and the National U. of Singapore, along with the Institute of Microelectronics at Peking U. in Beijing, Jujung Engineering Co. in Korea, and the U. of Texas. They avoided surface nitridization, which greatly improved mobility, according to H.Y. Yu.

Intel reported another approach to avoiding a 40%–50% electron-mobility degradation in HfO2/poly-Si gate stacks for nMOS transistors in a session on integrating metal gates with high-k dielectrics. S. Datta and co-workers reported building TiN gates on HfO2 dielectrics on a thin layer of tensile-strained silicon, deposited by ultrahigh vacuum CVD on a 1.5µm-thick GeSi layer that is compositionally graded and fully relaxed. These devices showed normal mobilities with three orders of magnitude less leakage than typical oxide gate dielectrics.

Improved interface quality, and thus more stable gate stacks with HfO2 dielectric, can be achieved by incorporating deuterium (D2O) during the atomic layer deposition (ALD) process, according to H.H. Tseng and co-workers at Motorola. Tests showed a much lower VT shift after constant voltage stressing, they reported.

Tests reported by A. Shanware, et al., at Texas Instruments and G.A. Brown, et al., of International Sematech, suggested that VT shifts are 10× bigger in HfO2 than in HfSiON dielectrics. Similar results were found by Matsato Koyama, et al., of Toshiba for HfSiON, which they termed the most promising of the high-k materials for commercial LSIs. Attendees at the conference suggested that it would be necessary to use ALD to deposit this material in order to get the proper molecular balance. The Toshiba group suggested that the improved breakdown phenomena observed even in sputtered films is probably due to the better homogeneity of the HfSiON microstructure.

Advances in low-k dielectrics and SOI

The long and difficult search for processable low-k dielectric materials continues, as shown in presentations made by researchers from Advanced Micro Devices (AMD), NEC Corp., and Taiwan Semiconductor Manufacturing Co. (TSMC).

AMD has moved low-k and silicon-on-insulator (SOI) technologies into high-volume production of nine-metal-layer microprocessors. David Greenlaw, manager, process integration, described how AMD researchers have overcome "several challenges" in developing technologies for producing nine-metal Opteron and Athlon 64 microprocessors.

"AMD's SOI and low-k technologies have reached maturity in high-volume manufacturing," Greenlaw stated. "In overcoming these challenges in wafer processing, we have achieved yield learning and performance-enhancement rates equivalent to or better than conventional technologies." The 130nm version of the nine-metal microprocessors has been in production for several months; shipments of the 90nm version will begin in the next few months.

A paper by NEC researchers (M. Tada, et al.) detailed how they developed 65nm Cu interconnect technology using a porous SiOCH film with a k value of 2.5 with sub-nanometer pores. An ultrathin, low-k (k = 2.7) organic silica film was used to coat the SiOCH and seal its pores, resulting in improved reliability and performance. The pore-seal technology was critical to success because it helped deal with the inherent problems of porous films — gas absorption, metal diffusion, and discontinuity of barrier metal.


Cross-sectional TEM of nine metal-layer Cu interconnect with porous low-k OSG (k≈2.5) and low-k etch stop (k≈3.0). (Source: TSMC)
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Another presentation described how TSMC researchers (Z.C. Wu, et al.) have integrated high-performance dual-damascene technology using a low-k etch stop (LES) of oxygen-doped carbide (k≈3.0) and a porous low-k dielectric (OSG, k≈2.5; see figure).

Results were impressive. The Cu dual-damascene interconnects with the LES exhibited superior interconnect RC delay (by 21%), 100% higher via-EM resonance, 100× lower line-line leakage at 125°C, and 5% faster device-operation speed compared to dual-damascene interconnects that used an etch stop of oxygen-doped carbide with a k value of ~4.5.

TSMC researchers also reported that they demonstrated functional device characteristics and 5% faster device operation speed of 90nm CMOS using the advanced LES, "indicating the feasibility of LES Cu dual-damascene interconnects at 90/65nm and beyond."

Novel memories, laser annealing

Chalcogenide phase-change memory technology, a candidate for next generation nonvolatile storage, was reviewed by Stefan Lai of Intel. Based on a GeSbTe (GST) alloy, these devices switch from an amorphous to crystalline state and back again with successive current pulses. The technology is already used with lasers in CD/DVD read-write disks. Efforts to reduce the programming current from above 1mA at the 180nm node to a few hundred µA, were described. While the current is reduced by scaling, other techniques, such as using nitrogen doping or an edge contact, were also noted. Phase-change memory devices promise fast read and write, low voltage, and moderate energy operation, and research shows they could be scaled at least to the 22nm node, according to Lai.

By using nitrogen and also modifying the structure of a cell of phase-change random access memory (PRAM), Samsung's Y.N. Hwang et al. reported lowering the writing current to 0.7mA. Adding a tungsten heater (as the bottom electrode) to the PRAM device enabled Hitachi researchers to achieve a 2 nsec read operation using a 50µA reset current, which is expected to make the memory suitable for 200MHz circuitry, according to N. Takaura et al.

Nonvolatile memory arrays consisting of organic materials sandwiched between orthogonal electrodes on top of conventional CMOS devices were described by R. Sezi et al., Infineon Technologies. Small cells can be deposited by vacuum evaporation or spin-coating, and also can be used in stacked layers to increase density. The memory cells could be deposited in vias between the electrodes to avoid crosstalk. Sezi reported that AFM investigations suggested the devices could be scaled down to <20nm, but improvements will be needed in switching voltage and reliability.

In future transistors, when shrinking to 50nm gates and below, rapid thermal annealing (RTA) of ultrashallow junctions will not be acceptable because of thermal diffusion of dopants and solid solubility limitations. Laser thermal processing (LTP) was employed by Akio Shima and co-workers at Hitachi Central Research Labs, in collaboration with Ultratech, to melt a sample for a few nanoseconds, significantly enhancing solubility without appreciable diffusion. Pulsed excimer lasers have not worked well for this application because they operate at frequencies highly absorbed by the silicon layer. Thus, the melting can cause deformation of fine patterns under the isolation oxide. By using a phase switch (PS) layer on top of the conventional laser absorber, the researchers were able to use an Nd:YAG pulsed laser instead, which has the property that reflectance changes sharply at a phase-switching temperature. Optimizing the switching temperature allows a self-limiting process that prevents over-melting of the silicon. Different junction depths were controlled at the same time, the group reported, and after LTP the absorber/PS stack was removed. Remarkable improvement in threshold voltage characteristics were achieved, according to Shima et al.

One of the most intriguing papers at IEDM was by Charles Lieber of Harvard, describing how he and his group were building novel devices onto single-crystal nanowires, including heterojunctions or superlattices. He showed a TEM image of a 3.5nm dia. silicon nanowire, and other heterostructure devices of GaAs/GaP and a radial core/shell nanowire of Ge/Si. Lieber said he is working with Intel on a Si HfO2 core/shell structure as well. These molecular-scale nanowires behave as single quantum structures with a finite number of carriers and unique physics, according to Lieber. Low temperature measurements showed no strong scattering centers over 400nm lengths, suggesting that the elastic mean free path is at least 400nm, he said.