Advanced device applications using single-wafer epitaxy
02/01/2004
The enabling capabilities of single-wafer epitaxial technology have quickly emerged since its introduction in the late 1980s. Originally adopted to address issues like layer-thickness uniformity or dopant incorporation, single-wafer epitaxy was used because gas depletion and temperature uniformity could be controlled much better than in batch-type systems. Single-wafer systems are also efficient development tools when it comes to cycle time and process changes.
The use of SiGe as a compound semiconductor and C doping to limit boron diffusion have been key milestones. Both technologies drastically improved the performance of heterojunction bipolar transistors (HBT) in the mid-1990s. This was followed by the introduction of selective growth of Si or SiGe to raise the source and drain areas of CMOS transistors, and more recently, strained Si and SiGe to enhance the channel mobility of CMOS transistors. Applications founded on epitaxy of silicon-based materials are still changing the landscape of IC manufacturing technology, and are enabling the necessary transistor-performance improvements as dimensional downscaling becomes more challenging and costly.
Heterojunction bipolar transistors
Thanks to continuous improvements in design and growth technology, HBT devices have revolutionized the wireless communication industry with unparalleled performance advances of higher speed at lower power. A record cut-off frequency of 350GHz was reported by the pioneer in this field, IBM, during IEDM in December 2002.
HBT epitaxial-growth technology is challenging because a base layer of only 10–40nm needs to be produced with very distinct requirements in terms of Ge-based band-gap engineering and B dopant incorporation. Such capabilities are available due to the design of the ASM Epsilon epitaxy system, which includes a rectangular-shaped quartz reactor chamber. The corresponding short residence time of the reactive gases allows the well-controlled manufacturing of very thin-layer structures with complicated composition and dopant profiles. In addition, the use of lamp heating and thermocouple temperature control makes processing over a 200–1200°C temperature range feasible.
The most advanced HBT structures also include an epitaxially grown emitter layer, for which the challenge is to grow defect-free layers without changing the B profile of the base layer. The surface oxide of the base layer needs to be "baked off" in H2 gas at a sufficiently low temperature within a relatively short time. For that reason, a dynamic bake process was developed by ASM, called E3 Solution, or Enhanced Epitaxial Emitter process. Figure 1 illustrates that there was no change to the B dopant profile and no interface defects using this process.
Elevated source and drain
The elevation of the source and drain areas of CMOS transistors becomes indispensable when junctions become shallower and sacrificial Si needs to be supplied to facilitate silicidation. In particular, for fully depleted transistors where ultrathin Si channels are used on an insulator oxide, the use of elevation is mandatory. Such elevation is made possible with a selective epitaxial-growth process, which makes it the first selective deposition process used in device manufacturing.
 Figure 2. Selective epitaxial growth of Si for the elevation of source and drain showing no facet formation and no deposits on the spacer or capping dielectrics. |
Many efforts in the development of selective epitaxial processes have resulted in solutions to problems such as loss of selectivity, facet formation, and area-dependent growth rates. The cross-section TEM of Fig. 2 shows a Si epitaxial layer, grown selectively, without facets and without Si deposits on the spacer or capping dielectrics. Loss of selectivity can almost always be related to inadequate cleanliness of the wafer surface. Implementation of state-of-the-art resist-removal and wafer-cleaning procedures are clearly needed for successful high-volume manufacturing.
Strained Si
The possibility of enhancing the channel mobility by using strained Si, and thereby increasing the transistor drive current, has been extensively studied and demonstrated. An interesting difference in approach is either to supply a blanket strained-Si wafer (before any other process occurred), or to induce strain locally (after the active area has been defined or even after the gate has been defined).
For blanket strained-Si wafers, a thick, graded SiGe buffer layer is grown to achieve lattice relaxation with a low dislocation density, which is then followed by the growth of a thin strained-Si layer. This widely accepted method may interest the wafer-supply industry.
 Figure 3. Selective growth of a thin, lattice-relaxed SiGe/SiGe:C layer structure in the recess-etched active area (R. Delhougne et al., Applied Surface Science, at press). |
For a local implementation of strain, other lattice strain engineering processes are being developed, which mostly require selective epitaxial growth. Figure 3 illustrates the use of a thin, selectively grown, lattice-relaxed SiGe/SiGe:C layer structure that serves as a basis for the selective growth of a strained Si layer. At the 2003 IEDM conference, Intel demonstrated that the selective growth of strained SiGe in the recess-etched source and drain area is an effective manufacturing technique to induce strain in the channel of pMOS transistors.
Conclusion
The applications discussed are only a few illustrations of the key role epitaxial growth is playing in the challenging landscape of device-manufacturing technologies, especially with rising use of SiGe and strained Si. Two to three nodes of the ITRS roadmap have been pulled in with the spectacular improvement of transistor performance obtained with epitaxial channel strain engineering. As a consequence, the integration of epitaxial technologies is also accelerating as fully depleted devices on insulator substrates are being developed. Selective epitaxy has been adopted by the most prominent IDMs as a manufacturable technology for 90nm and beyond as shown by 2003 IEDM conference papers [1, 2].
Acknowledgments
Additional authors of this article include N. Cody, P. Brabant, J. Italiano, P. Tomasini, and M. Bauer of ASM America. Epsilon and E3 Solution are registered trademarks of ASM International.
References
1. H. Park et al., IEDM, p. 634, 2003.
2. T. Ghani, et al., IEDM, p. 978, 2003.
For more information, contact Chris Werkhoven, VP of strategic marketing, at ASM America, 3440 East University Dr., Phoenix, AZ 85034-7200; e-mail [email protected].