High-frequency capacitance measurements monitor EOT of thin gate dielectrics
02/01/2004
Increasing measurement frequency and using a vector network analyzer permits accurate EOT measurements at thicknesses ≤0.9nm, aiding the move to smaller device dimensions and thinner gate oxides.
The decreasing thickness of gate dielectrics in CMOS processes presents a great challenge to the traditional capacitance measurements used for statistical process control. The capacitance value in the inversion or accumulation region of the capacitance-voltage (C-V) curve no longer has a simple relationship to the gate-oxide thickness. It is necessary to consider quantum mechanics and polysilicon depletion effects to determine oxide thickness from the C-V curve accurately [1, 2].
In addition, gate leakage increases exponentially as thickness decreases, due to tunneling of carriers through the ultrathin gate [3]. The gate capacitor becomes very lossy due to high leakage, and the gate capacitance measurement shows roll-off effects in both the inversion and accumulation regions of the C-V curve [4]. As a result, it's no longer possible to extract Cox directly and use it to monitor thickness variations in production. The roll-off behavior varies with the DC leakage of the gate, so that for two gate dielectrics with the same thickness and different leakages, different Cox results are obtained.
Some possible optimizations extend the use of the traditional C-V technique. Device-related roll-off effects in the C-V curve [5, 6] due to channel resistance and contact resistance could be modeled by a different equivalent circuit model and reduced by a new device layout. But some of the roll-offs are related to sub-optimal external setups, including cabling, connectors, and probe station setup [7]. By optimizing cabling, connectors, probe card, and DUT layouts, it's possible to monitor process variation of equivalent oxide thickness (EOT) to 1.3nm (suitable for the 90nm technology node) using an LCR meter at frequencies to 100MHz, or to <0.9nm using the RF C-V approach.
As previously discussed, the challenge of using an LCR meter for monitoring EOT variation involves getting correct capacitance measurements on very leaky gate materials. The effect of gate leakage in capacitance measurement can be represented by the dissipation factor (D). As gate-oxide thickness decreases to <2nm, it is not unusual to see gate capacitance with D >10 or even 100 at 1MHz. The direct result of large D is a roll-off of the C-V curve in the inversion or accumulation region. Sometimes the measured capacitance value is negative [8].
It's important to understand how measurement error is related to D. For a parallel RC circuit, the capacitance error can be simplified as:
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where E0 denotes basic measurement error on a perfect capacitor
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and Θ = cot-1 D.
Equation 1 suggests that the measurement error is linearly dependent on D. When D becomes large enough, the phase error is amplified by D and becomes the dominant source of error. Equation 2 shows that D decreases with frequency. The frequency used will be limited by instrumentation and DUT structure layout. The LCR meter most commonly used in this application has an upper frequency limit of 1MHz. At the 1MHz D level, phase error must also be reduced to achieve minimum measurement error.
Another way to minimize error in capacitance measurement is to reduce D dramatically by increasing the frequency of the measurement by a factor of 1000 to 10,000. This requires optimization of the measurement system for gigahertz signals, RF design rules in device layouts, and new measurement methods that include device-specific calibration and optimizing the signal path, because signal integrity is key to getting reasonable measurements for both approaches.
Capacitance measurement at high frequency (<1MHz)
Integrating an LCR meter with an automatic parametric tester (APT) for EOT monitoring at up to 1MHz has a clear cost advantage for current technology nodes. The LCR meter has been widely used in parametric tests for EOT and other monitoring applications. By adding a dedicated pathway and a switch with enhanced AC ground, it's possible to measure gate oxide down to 1.5nm without modifying those parametric tests not related to EOT. Increasing frequency capability of the LCR to 100MHz will extend valid measurement to 1.3nm. (Some of the technical issues are explained in "Measuring EOT with an LCR meter at 1MHz.")
It is well known that some roll-offs in C-V curves are due to the channel resistance of the MOSFET [6]. Figure 1 shows an example of capacitance measurements on three transistors of different gate lengths with normalized capacitance value, and clearly shows the channel resistance-induced roll-off effect. Even though proper device modeling can compensate for this effect, it is not desirable in a production environment. It's a good idea to use a short-channel transistor to minimize channel resistance-induced roll-off. With a small-area transistor, the fringing capacitance is relatively large, so it can be subtracted by measuring capacitances with two different gate areas. The requirement of measuring additional devices and reduced accuracy on small-area transistors are major drawbacks in trying to extend the use of LCR beyond the 90nm node.
RF capacitance measurement
If increasing frequency reduces D and improves accuracy, why not use an LCR meter that works up to 100MHz? This helps, but brings with it another set of problems, and requires a full calibration set, including phase, open, short, and load calibration. At the same time, the product of phase-measurement accuracy and D limits performance; therefore, it can only extend measurement capability one or two technology nodes further. The answer is to increase frequency to 1GHz and higher, the point of maximum Q, and use the RF technique to measure capacitance. At such frequencies, D will remain relatively small for the foreseeable future (according to the International Technology Roadmap for Semiconductors). Conductance due to leakage ceases to be an issue.
The RF capacitance of the DUT is derived from the complex conductance
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which is calculated from S-parameters measured on a two-port network. A vector network analyzer (VNA) is used to measure the RF scattering parameters. The impedance of the DUT can be calculated from reflection parameters S11 and S22
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with Z0 = 50Ω. The frequency of measurement is selected so that the AC impedance of the DUT is close to 50W, because the measurement accuracy of a vector network analyzer is optimized around 50Ω. For example, a 1pF capacitor has 50Ω impedance ≈3GHz.
The parasitics embedded in the measurement system and the DUT represent some of the technical difficulties involved in using RF measurement. Figure 2 shows a simplified circuit model of a real transistor. The goal of RF capacitance measurement is to get Cox; however, Cox is surrounded by imperfections in the physical device. Those imperfections include overlap capacitance between the gate contact and the source/drain well, gate resistance (due to polysilicon), lead inductance (from DUT to contact pads), contact resistance (between probe needle and contact pads), and channel resistance (mentioned earlier). Some of the imperfections can be extracted by the de-embedding technique, especially the effects of contact resistance, lead inductance, and parasitic capacitance. DUT measurement results are corrected by subtracting those measured on de-embedding structures. Typical de-embedding structures include open, short, and through. For short de-embedding,
Z = Zmeas - Zshort
for open de-embedding,
Y = Ymeas - Yopen
and for through de-embedding,
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Combinations of two or more of the de-embedding techniques can be used. It is common to use open and short de-embeddings together to correct both parasitic capacitance and contact resistance. Sometimes, open and through are used together when the series inductance of the DUT is not optimized.
One basic assumption of RF C-V measurement is that the characteristic impedance of the system's transmission line is 50Ω. The closer the impedance of the transmission line is to 50Ω, the better the measurement result. The device layout on the wafer should be adjusted to match the transmission line impedance. A ground-signal-ground structure is required for RF measurement. As mentioned previously, channel resistance effects will show up in C-V measurements on long channel devices, especially at higher frequencies. Small transistors should be used for RF capacitance measurements. To achieve better signal-to-noise ratio, many small-area transistors can be connected in parallel to make a large device. More details about design of test structures for RF C-V measurement are in Ref. 9.
Several precautions are necessary to maintain accuracy. One is minimizing contact resistance variation between consecutive probe contacts. For example, if the DUT has a characteristic impedance of 100KΩ at 1MHz, a 1Ω variation in contact resistance will cause only a 0.01% error. However, the characteristic impedance of the same device drops to 100Ω at 1GHz, so that same 1Ω variation in contact resistance will induce a 1% error. Keeping the probe needles clean and free of aluminum oxide buildup should be an automated attribute of the measurement system.
Accurate measurements require calibrations down to the probe tip. A full calibration set includes open, short, through, and load calibrations. Calibration compensates for imperfections in the transmission line, including parasitic capacitance and lead inductance on the probe card and connectors. Calibration cannot compensate for contact resistance, however, because the contact resistance between the probe needle and the gold contacts on the calibration substrate is not the same as that between the probe needle and the aluminum pad on actual wafers under test.
 Figure 3. RF C-V measurement on a 1.3nm gate oxide. |
Figure 3 shows RF C-V measurement results on a 13Å gate oxide at 2.4GHz. A 20MHz C-V measurement using an LCR meter is also plotted as reference.
Conclusion
By increasing measurement frequency into the gigahertz region and using a vector network analyzer, it's possible to get accurate EOT measurements at thicknesses of 0.9nm and less. This helps remove a major hurdle in the race to smaller device dimensions and thinner gate oxides.
References
- N. Yang, W.K. Henson, J.R. Hauser, J.J. Wortman, "Modeling Study of Ultrathin Gate Oxides Using Direct Tunneling Current and Capacitance-Voltage Measurements in MOS Devices," IEEE Trans. on Electron Devices, Vol. 46, p. 1464, July 1999.
- K.F. Schuegraf, et al., "Impact of Polysilicon Depletion in Thin Oxide MOS Technology," Proc. VLSI-TSA, p. 86, 1993.
- Y. Shi, T.P. Ma, S. Prasad, S. Dhanda, "Polarity-Dependent Tunneling Current and Oxide Breakdown in Dual-Gate CMOSFETs," Electron. Dev. Lett., Vol. 19, p. 391, October 1998.
- C.H. Choi, et al., "Capacitance Reconstruction from Measured C-V in High Leakage, Nitride/Oxide MOS," IEEE Trans. on Electron Devices, Vol. 47, p. 1843, October 2000.
- K.J. Yang, C.M. Hu, "MOS Capacitance Measurements for High-Leakage Thin Dielectrics," IEEE Trans. on Electron Devices, Vol. 46, p. 1500, July 1999.
- D.W. Barlage, et al., "Inversion MOS Capacitance Extraction for High-Leakage Dielectrics Using a Transmission Line Equivalent Circuit," IEEE Electron Device Lett., Vol. 21, p. 454, September 2000.
- H. Suto, et al., "Methodology for Accurate C-V Measurement of Gate Insulators below 1.5nm EOT," extended abstract of the 2002 Intl. Conf. on Solid State Devices and Materials, p. 748, 2002.
- Y. Okawa, H. Norimatsu, H. Suto, M. Takayanagi, "The Negative Capacitance Effect on the C-V measurement of Ultra Thin Gate Dielectrics Induced by the Stray Capacitance of the Measurement System," Proc. ICMTS, p. 197, 2003.
- J. Schmitz, et al., "Test Structure Design Considerations for RF-CV Measurements on Leaky Dielectrics," Proc. ICMTS, p. 181, 2003.
Carl Scharrer is a principal industry consultant with Keithley Instruments Inc. His prior employment with Texas Instruments, Fairchild, and Motorola spanned 20 years and involved design, test, and yield enhancement of high-performance digital ICs. He can be reached at Keithley Instruments Inc., 28775 Aurora Rd., Solon, OH 44139; e-mail [email protected].
Yuegang Zhao received his BS in physics from Peking University, Beijing, China, and his MS in semiconductor physics from the University of Wisconsin. He is a senior applications engineer with the Semiconductor Business Group of Keithley Instruments Inc. in Cleveland, OH. Zhao has five years of experience in semiconductor physics.
Measuring EOT with an LCR meter at 1MHz
Cabling is very important in C-V measurement. The overall cable length in the system must be kept as close as possible to the calibration length of the LCR meter. Any deviation will introduce phase error.
Experience shows that capacitance measurements with small D (around 0V) are not affected very much by variations in cable length; when D is small, the overall measurement error is dominated by E0, according to Eqn. 1, and phase error does not play a leading role. But when D is large, as in the inversion region, the cable-induced phase-error effect becomes significant. When the calibration length is close to the actual physical one, the inversion region is reasonably flat. However, when the calibration length is shorter than the physical length, the curve starts rolling up. When the calibration length is longer than the physical length, the curve rolls off.
Another factor is the shield jumper. Proper operation of an LCR meter requires that the shields of the coaxial cables be properly connected as close to the DUT as possible. These shields provide a current return path that compensates for parasitic inductance from the cabling. If the cable shields are not tied properly, close to the DUT, there will be some parts of the cables (close to the contact point to the DUT) not returning current in the shield. This results in extra phase errors due to the inductance effect.