Technology News
01/01/2004
Software helps explore immersion lithography
New simulation software helps explore the impact of polarization in very-high NA scanners by evaluating the image on the wafer's resist. The software package, designated SOLID-CTM 6.2 and developed by SIGMA-C, calculates the resist's image intensity.
For now, the software models the wafer topography and how a uniform resist would flow, and also models liquid immersion lithography, one of the industry's latest hot options (Figs. 1 and 2). By 1Q04, the company expects to model arbitrary topography on a wafer, and that could include the ability to model nanobubble formation.
 Figure 1. Liquid immersion lithography example: 55nm half-pitch lines and spaces, with λ = 193nm, NA = 1.3, σ = 0.63, COG, annular illumination. |
Until the advent of hyper-NA systems (NA<0.83), optics simulation was relatively simple. It was not especially important to know the location of the diffraction orders of light coming from the lens to the wafer or the polarization. In hyper-NA tools, however, the effects of polarization on light diffracted to large angles are huge [1].
 Figure 2. Liquid immersion lithography example: 80nm contacts over oxide wedge; λ = 193nm, NA = 1.3, σ = 0.4, COG, circular illumination. |
"In special situations associated with alternating aperture phase shift masks, transverse magnetic polarization of the source will result in an image contrast of <0.3, whereas transverse electric polarization will have image contrast ≈1," explains Peter Brooker, applications support engineer at SIGMA-C (Fig. 3).
While the light source is typically unpolarized, the transmission of the two polarizations into the resist can also be different. The net resist exposure must be calculated as the proper sum of the two polarizations. The parameters of ARC layers and resist films also depend on incidence angle and polarization in ways that require computer optimization.
Aside from the industry's need for a technology suitable to take it from 193 lithography to either EUV or some other NGL choice, the impetus to go from high-NA "dry" lithography to immersion is that in today's steppers, you can't just make a larger lens column to image finer and finer geometries.
"If you did, the rays at the edges of the lenses would be totally internally reflected," explains Brooker. "The transmission of light at the edges of the lens would then go to zero. However, if you put water between the last lens surface and the wafer, then you can get those edge rays down to the wafer." This can result in effective NAs>1.0.
However, such large NAs make the polarization effects even worse in immersion lithography; the contrast formed by the very large angle rays can vanish or even be reversed by polarization effects when the light propagates through the resist at 45°. Immersion lithography uses these large angle rays to form the finest images and thus simulators that attempt to model immersion lithography must be sensitive to polarization effects.
Reference
1. Peter Brooker, "Using Location of Diffraction Orders to Predict Performance of Future Scanners," SIGMA-C, Campbell, CA, 23rd Annual BACUS Symposium on Photomask Technology, 8–12 September, 2003, Monterey, CA.
Intel announces high-k/metal gate breakthrough
Intel Fellow Robert Chau presented results of Intel Corp.'s high-k/metal gate transistor development at the International Gate Insulator Workshop in Tokyo, Japan, in early November. The new high-k gate materials are needed to reduce current leakage as device dimensions shrink and transistor gate dielectrics become thinner.
For five years, Chau led a team working on solving the problems inherent in the search for new gate dielectric materials and integrating them with metal gate electrodes.
According to Ken David, director of components research at Intel, the most significant advance in eliminating voltage pinning and phonon scattering was selecting correct materials for the gate electrodes. Intel had an internal model of what caused these problems; when the correct materials were selected, the problems disappeared.
 High-k dielectric reduces leakage substantially. |
The metals — which remain confidential — must have work functions that match the properties of the polysilicon material they are replacing. The metals will be used in combination with the new high-k gate dielectrics for both PMOS and NMOS transistors.
The company presented a transistor curve taken from an 80nm NMOS transistor built using the new process and materials that had an Ion = 1.5mA/μm and an Ioff = 43nA/μm, at a drain voltage = 1.3V. The company later released updated performance data for its high-k metal gate NMOS.transistor: a drive current of 1.66mA/μm, Ioff = 37nA/μm (Vcc = 1.3V).
David declined to identify the high-k material that was selected, and also did not identify the supplier of the ALD equipment expected to be used in production. He did say there were no special manufacturing challenges to be overcome in order to use ALD to make the new transistor. The company does not currently use ALD in its manufacturing processes, but the process technology is being evaluated for other steps in the company's manufacturing flow.
Because Intel has what David described as a fairly large materials group that works closely with R&D to ensure that selected materials will be available when needed, he foresees no problems with availability. David also characterized any changes that will be needed to the manufacturing process as being "cost neutral" — essentially changing out one type of tool for an ALD system. He added that some process steps would be going away (e.g., growing oxides, polysilicon deposition).
According to Intel's roadmap, the new transistors are expected to be in production by 2007 at the 45nm technology node — when it expects to use 193nm/high-NA lithography. David noted that by 2007, Intel anticipates its microprocessors will contain around 1 billion transistors. A Pentium 4 microprocessor has 55 million transistors.
U. of Illinois researchers create world's fastest transistor — again
Researchers at the U. of Illinois at Urbana-Champaign have broken their own record for the world's fastest transistor. Their latest device, reported to have a frequency of 509GHz, is 57GHz faster than their previous record-holder and could find use in applications such as high-speed communications products, consumer electronics and electronic combat systems.
"The steady rise in the speed of bipolar transistors has relied largely on the vertical scaling of the epitaxial layer structure to reduce the carrier transit time," said Milton Feng, the Holonyak professor of electrical and computer engineering at Illinois, whose team has been working on high-speed compound semiconductor transistors since 1995. "However, this comes at the cost of increasing the base-collector capacitance. To compensate for this unwanted effect, we have employed lateral scaling of both the emitter and the collector."
Feng and graduate students Walid Hafez and Jie-Wei Lai fabricated the high-speed devices in the university's Micro and Nanotechnology Laboratory. Unlike traditional transistors, which are built from silicon and germanium, the Illinois transistors are made from indium phosphide and indium gallium arsenide (see figure).
 The world's fastest transistor reportedly has a frequency of 509GHz. |
"This material system is inherently faster than silicon germanium, and can support a much higher current density," Feng said. "By making the components smaller, the transistor can charge and discharge more quickly, creating a significant improvement in speed."
Another technique the researchers employed to boost transistor speed used a narrow metal bridge to separate the base terminal from the device connector post.
Faster transistors would enable the creation of faster computers and video games, more flexible and secure wireless communications systems, and more rapid analog-to-digital conversion for use in radar and other electronic combat systems.
"Further vertical scaling of the epitaxial structure, combined with lateral device scaling, should allow devices with even higher frequencies," Feng said. "Our ultimate goal is to make a terahertz transistor."
The Defense Advanced Research Projects Agency funded the work.