Issue



A perspective on enhancing mobilities


01/01/2004







Key metrics for enhanced MOSFET performance are increased speed, increased drain current at saturation (Idsat), and reduced capacitance equivalent thickness (CET) in inversion [1]. The maximum attainable Idsat for silicon MOSFETs has been noted to be limited by the thermal injection of carriers from the source into the channel, with Ge suggested as a more efficient injecting material than Si (M. Lundstrom*). Nevertheless, it is advantageous to enhance the carrier mobility beyond the universal mobility curves to achieve future speed and Idsat device metric goals, as was extensively discussed at the 2003 IEDM.

Inducing a tensile strain in the channel can enhance both the electron and hole mobility beyond the universal mobility curves. For optimal CMOS performance, it is desirable to increase the hole mobility more than the electron mobility so that the final, enhanced values of the two mobilities are more equal than for unstrained silicon. Numerous techniques have been shown to induce strain in the channel including the influence of a tensile (localized) film above the channel (A. Shimizu et al. and K. Ota et al.), shallow trench isolation (STI) induced stresses (Y.G. Wang et al.) as well as the role of the source/drain silicide (A. Steegen).


(a) Electron [4, 5] and hole enhancement [5, 6] factors and (b) schematic illustration of tensile induced strained silicon layer, courtesy of Patricia Mooney [8] (IBM Corp.). Reproduced with the permission of the American Institute of Physics [1].
Click here to enlarge image

The epitaxial growth of silicon on underlying Si:Ge layers, however, is a current leading edge methodology that may be utilized, as appropriate, in conjunction with one of the techniques noted above. There has been steady progress in understanding the underlying epitaxial strain mechanisms. Several complementary techniques to enhance the electron carrier mobility in the n-channel have been reported, including the incorporation of an epitaxial strained silicon film on Si:Ge layers. In one case, for example, the biaxial in-plane tensile strain arises as a result of the lattice mismatch between the epitaxial Si and the underlying uniform composition, relaxed Si(1-x)Gex epitaxial film grown on a compositionally varied Si(1-y)Gey epitaxial film, where y<x in the first film and x = y in the adjacent film for n-channel devices (E.A. Fitzgerald et al. and J. Welser et al. [2]). Other cases include slightly different strained configurations for p-channel devices as discussed by K. Rim et al. [3] as well as strained Ge channels (C.O. Choi et al. and H. Shang et al.).

The deconvolution of mobility, however, is still riddled with numerous unresolved issues. The detailed analysis from capacitance-voltage (CV) and current-voltage (Id-Vd) curves to determine the effective surface mobility or transconductance has re-emerged as a critical issue (W.J. Zhu et al.). It is well accepted that at low-effective surface electric field, scattering is dominated by unscreened (no inversion layer free carriers) ionized dopant scattering centers in silicon. At high-effective surface electric field, surface acoustic phonons and surface microroughness are the critical contributors. The latter contribution is generally represented by the product H×L, where H is the height of the surface undulation and L is the undulation's correlation length as noted by D.S. Jeon and D.E. Burk as well as J. Hauser and colleagues. Recently, M.V. Fischetti and colleagues have postulated that remote scattering by high-k gate dielectric optical phonons, coupling with the silicon channel, degrades the surface mobility. The mobility, µ, is represented as

µ = qτ/m*

where q = absolute value of electronic charge; τ = reciprocal of the scattering rate; and m* = conductivity effective mass. The presence of an interfacial oxide reduces optical phonon coupling to the silicon channel, at the expense of increasing the dielectric stack's CET.

For high-k gate dielectrics, additional sources of scattering leading to mobility degradation have been deduced by detailed experiments, although a theoretical basis for these sources continues under development. These include interfacial and high-k gate dielectric bulk traps (L. Pantisano et al. and G. Bersuker et al.), crystalline inclusions in amorphous high-k gate dielectrics (T. Yamaguchi et al.), N, Al and other elemental interface scatterers, as well as remote scattering due to the gate electrode (G. Timp et al.).

Band-engineered MOSFETS such as the surface strained silicon structure have received significant attention for increasing the carrier mobility and Idsat (E.A. Fitzgerald et al., J. Welser et al. [2]. and K. Rim et al. [3]). The electron mobility enhancement (relative to the unstrained case) of 1.6–1.8 has been reported for a Ge atomic content of about 20% (Fig. 1) [4, 5], even up to high-effective surface electric fields beyond 1MV/cm (K. Rim et al.), although the reduction of surface microroughness may also be operative ([4, 5] and K. Rim et al.). Comparable n-channel Idsat enhancements have been reported for long-channel devices (M. Jurczak et al.), whereas the enhancement degrades to <50% in the case of short-channel devices (Y. Taur and T.H. Ning). The hole mobility enhancement can apparently be as large as 2.5, requiring a Ge content of ~35 atomic% [5, 6] as seen in the figure, which may not be unexpected considering the increased hole mobility of germanium as compared to silicon [7].

Figure 1 also schematically illustrates the increased lattice constant of the strained silicon on a relaxed epitaxial Si(1-x)Gex film, the latter material straining the subsequently epitaxially deposited silicon (channel layer) in a biaxially tensile manner. This splits the silicon conduction band's six-fold degenerate electron Δ orbitals, lowering the energy of the out-of-plane Δ2 orbitals, relative to the Δ4 in-plane orbitals, by about 200meV (Y.H. Xie). The occupancy of the Δ2 orbitals is thereby increased and this leads to a lowered conductivity effective mass, resulting in an increased electron mobility. Another, perhaps more important factor, is the reduced intervalley scattering, which also enhances the electron mobility. Assessment of the thermal stability of the residual strain in such films after IC fabrication is most important [5].

The hole mobility is more complicated due to the degeneracy of the light- and heavy-hole bands at k = 0 as well as the split-off band at k = 0. The tensile strain splits the silicon valence-band degeneracy, lowering the light-hole energy band relative to the heavy-hole band by ~77meV, and lowering the effective mass of both light-hole and heavy-hole bands (D.K. Nayak). Here, also, reduced intervalley scattering effectively increases hole mobility. For the hole situation, these observations have been reported for both biaxially tensile and compressive stresses (K. Rim et al.).

By engineering the controlled growth rate of the compositionally varied epitaxial Si(1-y)Gey and, thereby, minimizing the 60° misfit dislocation nucleation such that the threading dislocations are < 5×105/cm2, each subcomponent layer of the stack is relaxed to an intermediate lattice constant, reducing the misfit dislocation array during growth. Nevertheless, the underlying misfit dislocation array can affect the local epitaxial growth rate of the subsequent epitaxially deposited uniform composition, relaxed Si(1-x)Gex film as well as the strained silicon layer. Accordingly, chemical-mechanical polishing (CMP) has been used to reduce any residual crosshatch surface microroughness prior to deposition of the strained silicon layer, which could also affect subsequent photolithography processes (M.T. Currie et al. and K. Sawano et al.). The controlled introduction of misfit dislocation arrays and CMP results in a high-quality SiGe buffer layer for the epitaxial deposition of the strained silicon layer (typically 15–20nm).

A variety of Si:Ge strained configurations for enhanced hole mobility beyond the universal curve, in combination with one of the enhanced electron mobility methodologies, may be utilized for more effective equalization of the hole and electron mobilities. Also, the deposition of strained silicon on a high-quality SiGe buffer layer on silicon-on-insulator (SOI) [5] as well as the deposition of strained silicon directly on SOI offer a host of alternative structural configurations under consideration. In these SOI cases, both partially depleted and fully depleted structures can be fabricated (M. Bulsara et al.).

Significant integration issues and manufacturability, compatibility with SOI, and fabrication cost are important mitigating issues that need to be addressed [1]. Nevertheless, strained silicon clearly shows promise as a technology that can help enhance transistor performance down to the 18nm technology generation.

Acknowledgments

The authors appreciate discussions and use of a number of figures for both original manuscript and oral presentation from a number of our colleagues, comprehensively listed [1].

References


  1. H.R. Huff, P.M. Zeitzoff, "The 'Ultimate' CMOS Device: A 2003 Perspective (Implications for Front-End Characterization and Metrology)," 2003 International Conference on Characterization and Metrology for ULSI Technology, (ed. D.G. Seiler et al.), AIP Conf. Proc., 683, pp. 107–123, 2003.
  2. J. Welser, J.L. Hoyt, J.F. Gibbons, "NMOS and PMOS Transistors Fabricated in Strained Silicon/ Relaxed Silicon-Germanium Structures," IEDM, pp. 1000–1003, 1992.
  3. K. Rim, J. Welser, S. Takagi, J.L. Hoyt, J.F. Gibbons, "Enhanced Hole Mobilities in Surface-Channel Strained-Si p-MOSFETs," IEDM, pp. 517–520, 1995.
  4. S. Takagi, J.L. Hoyt, J.J. Welser, J.F. Gibbons, "Comparative Study of Phonon-Limited Mobility of Two-Dimensional Electrons in Strained and Unstrained Si on Metal-Oxide-Semiconductor Field Effect Transistors," J. Appl. Phys., 80, pp. 1567–1577, 1996.
  5. P.M. Mooney, "Materials for Strained Silicon Devices," International Journal of High-Speed Electronics and Systems, 12, pp. 305–314, 2002.
  6. R. Oberhuber, G. Zandler, P. Vogel, "Sub-band Structure and Mobility of 2-D Holes in Strained Si/SiGe MOSFETs," Phys. Rev., B 58, pp. 9941–9948, 1998.
  7. H.R. Huff, "Semiconductors, Elemental–Material Properties," Encyclopedia of Applied Physics, (ed. by G.L. Trigg), 17, pp. 437–475, 1996.
  8. P.M. Mooney, S.H. Christiansen, J.O. Chu, A. Grill, "Strain-Relaxed SiGe Buffer Layers With Low Defect Density and Surface Roughness," APS Meeting, March 3–7, 2003, Paper P8–2.

Adapted from material originally presented at the 2003 International Conference on Characterization and Metrology for ULSI Technology (March 24–28, 2003), H.R. Huff and P.M. Zeitzoff, ed. D.G. Seiler et al., AIP Conference Proceedings, 683, pp. 107–123, 2003.

*All authors mentioned above in text without reference numbers are from this work by H.R. Huff et al.

Howard Huff, International Sematech, 2706 Montopolis Drive, Austin, TX 78741; ph 512/356-3334, e-mail [email protected].