Implementation of CVD low-k dielectrics for high-volume production
01/01/2004
Overview CVD-based carbon-doped silicon oxides were developed for low-k applications in AMD Opteron and AMD Athlon 64 microprocessors. After resolving problems specific to low-k integration, yield and product-performance enhancement rates were equivalent to or better than those seen in conventional technologies.
The continued drive of ULSI device scaling has produced circuits in which the interconnect signal delay exceeds the gate delay. To achieve circuit speed enhancements, AMD has utilized copper interconnects for three generations of microprocessors. The last two generations have incorporated low-k interlayer dielectric (ILD) materials with Cu to further reduce RC delay as well as overall power consumption.
The low-k process technologies were developed for production of AMD Opteron and AMD Athlon 64 (64bit) microprocessors. The AMD64 processor uses a two-level cache-based architecture. The L2-cache contains 1Mb of on-die storage organized as 16-way set associative. The AMD64 also provides several power-saving states and is built on a silicon-on-insulator (SOI) substrate for lower thermal output levels, using a nine-level Cu interconnect backend technology with CVD low-k dielectrics. Tungsten-filled substrate contacts maintain the wafer substrate at ground potential during chip operation. Within the nine-metal Cu interconnect hierarchy are two power-planes (M5, M8) to ensure good Vcc and Vss distribution across the chip.
The implementation of low-k dielectrics at AMD's FAB30 required close collaboration between AMD and its low-k supplier, Applied Materials, to overcome various manufacturability and integration issues. These included reducing defects to a level equivalent to a fluorinated silicate glass counterpart design, optimizing film mechanical properties, resolving adhesion and packaging issues, and improving productivity parameters. The result is a manufacturable nine-metal layer low-k/Cu microprocessor design that is now in volume production at the 130nm node, with the transition to 90nm design rules expected to begin early this year.
Cu/low-k interconnect
Though numerous low-k alternatives exist today, development was focused on CVD-based carbon-doped silicon oxides (SiCOH). With fluorinated silicate glass (FTEOS) already in production, extending CVD technology to low-k was preferable because it enabled the re-use of existing CVD systems and manufacturing knowledge gained from those tools.
The intermetal dielectrics for the nine-level Cu back-end-of-line (BEOL) of the 130nm and 90nm processes employ both SiCOH and FTEOS ILDs (Fig. 1). Silicon carbide (SiC) is used as the low-k barrier dielectric and etch-stop layer with the SiCOH. The dielectrics for the power-planes and the last metal level are undoped silicate glass. Single damascene is used for 130nm, and dual damascene VFTL approach is used for 90nm with standard 248nm and 193nm lithography for the most critical layers. A Ta barrier metal gives good reliability, low via resistance, and excellent in-line defectivity. Figure 1 shows the completed backend hierarchy and schematic for the AMD Opteron processor.
Low-k integration
The low-k ILD film [2, 3] has a nominal k value of 2.9. Additionally, a SiC material with a k value of 4.8 was used for the dielectric Cu barrier. Both films fulfill all critical mechanical, thermal, and electrical properties and requirements for an integrated multilevel manufacturing process.
 Figure 2. CVD low-k ILD in-film particles and thickness uniformity data show excellent manufacturability across multiple systems. |
Hardness and modulus, which are good indicators of a material's CMP and packaging manufacturability, are reduced with low-k materials due to their porosity and film composition. These properties must therefore be optimized to ensure successful integration. The modulus of the low-k film is 10±2GPa, ~4× harder than typical SOD films (<3GPa [1]). For a modulus of ≤4GPa, interfacial delamination as well as cohesive failures can occur after CMP of low-k films [1]. Ongoing efforts have served to optimize the mechanical strength of our low-k material, which has proven to be sufficient for multilevel integration and packaging.
Adhesion is another major concern with low-k materials. Prior to the SiC barrier film's deposition, it is important to remove copper oxide (CuO) from the Cu surface to ensure good adhesion between Cu and the next ILD. CuO can lead to poor electromigration (EM) and an increase in via resistance if not removed before metal deposition. Single-wafer architecture enables a proprietary in situ CuO treatment prior to the SiC barrier film's deposition, with minimal impact on throughput. From past experience with silicon nitride (SiN), an adhesion strength >10J/m2 is needed to ensure good EM and reliability. Adhesion or fracture energies of our Cu-barrier interface were measured with the four-point bending technique. Compared to the untreated interface (3J/m2), also tested by a 4-point bending method, adhesion of the treated barrier to Cu was improved to >10J/m2, the minimum adhesion required.
Manufacturing performance
After the introduction of the low-k and dielectric barrier films into pre-production, increased defects and reduced chamber uptime were observed compared to those of conventional ILD deposition processes (oxide, fluorinated oxide, nitride, etc.). These problems increased die defectivity on device wafers, as well as particle build-up in the process chambers.
Optimizing the deposition and the subsequent in situ process chamber dry-clean step was necessary to reduce and maintain low defectivity. Chamber conditions and cleaning of carbon-containing low-k films has proven to be particularly important in achieving repeatable film performance. The single-wafer processing architecture provided the unique capability to perform high-productivity in situ cleans, either after every wafer or an interval of wafers, while ensuring the same chamber environment during deposition. The enhanced clean process was capable of running multiwafer cleans for high cleaning efficiency and low defectivity. The chamber-cleaning frequency was also optimized for maximum system throughput based on the number of chambers used.
 Figure 3. M2 sheet rho, for example, is stable in both backend technologies. |
With these improvements, the low-k unit processes delivered good manufacturability, achieving equivalent film and defectivity performance to the previous production baseline with FTEOS. Defect performance was equivalent to that of conventional ILD films, including FTEOS. SiCOH in-film particle performance for defects measured at >0.20µm was shown to be low and comparable to that of FTEOS (Fig. 2). Additional manufacturing performance indicators were also improved. The mean-wafers-.between-cleans metric improved from a few thousand wafers to >20,000 wafers/chamber.
Although defectivity on blanket film particle monitors showed similar performance to the production baseline, in-line defectivity of the overall Cu/SiCOH BEOL process remained higher, requiring further investigation. Characterization of the defects showed that they were coming from the bevel edge of the wafer. The cross-section of the wafer bevel showed several defect sources from the wafer edge, the outer bevel, and even the bevel backside. These defect sources were all associated with layer stacks on the wafer edge, which occur only in the edge exclusion zone for most processes. The varying edge exclusions of the backend deposition, etching, and planarization operations caused an incompatibility, resulting in poor adhesion of the low-k/Ta stack to Si. Low-k process tuning to better control the deposition at the bevel edge successfully solved this problem. In-line defectivity measurements after Cu seed-layer deposition over the last year reflected this improvement. The product yield increase has corresponded well with the defect reductions. This SOI/low-k technology now runs with a yield equivalent to that of the FTEOS baseline.
Electrical performance of Cu/low-k interconnect
Stability of the interconnect parameters requires special attention with CVD low-k films to achieve good Cu/low-k electrical performance. The lower physical density of ILD material produces both the desired low-k characteristics and lower mechanical stability during CMP. With CMP, care must be taken to avoid polishing into the low-k material since the high polish rate with standard slurries may be difficult to control, leading to undesired local pattern-dependent sheet-resistance variation of the interconnects. Implementation of the low-k dielectric shows stable M2 sheet resistance, as illustrated in Fig. 3. The delta in the sheet-resistance average for the FTEOS and SiCOH trend charts is caused by different target settings in metal thickness for these different products. Stable sheet-resistance trends allow consistent RC product comparisons between the FTEOS and low-k flows. An ~17% reduction in RC product is shown in Fig. 4 for a large M2 comb-serpentine test structure.
Reliability and low-k
 Figure 4. The Cu/low-k backend shows a 15–20% reduction in RC from FTEOS/SiN for an in-line test structure. |
Key components of the process reliability qualification for the AMD64 products included EM tests, stress migration tests, bias temperature storage, and product-level temperature cycling. The introduction of a low-k film included fundamental changes in the ILD film properties, as mentioned previously. The effect of lower mechanical strength and fracture toughness on reliability was of particular concern, resulting in a thorough study of the chip-package interaction. Temperature cycling tests in the temperature range from -55 to +125°C were done up to 1000 cycles without any fails. In addition, life tests, highly accelerated stress and bake tests, as part of the product qualification, were successfully completed.
Electromigration was also characterized. As noted earlier, optimization of the dielectric barrier layer and CuO removal were both identified as important factors for superior EM performance [4, 5]. The dielectric Cu barrier layer must be dense enough to protect the underlying Cu against any undesired species, especially at the elevated temperatures that typically occur in subsequent processing steps. The final EM performance was shown to have an even higher lifetime at accelerated test conditions than baseline FTEOS/SiN samples. Failure analysis of the failed EM samples with SiCOH/SiC dielectric (Fig. 5) showed failure modes similar to the ones observed in the baseline with FTEOS/SiN dielectrics. Wafer-level reliability (WLR) monitoring was employed in addition to the standard packaged EM and SM [6] reliability tests. Figure 6 shows a trend chart of WLR lifetimes, indicating good stability over many weeks of processing.
Expected challenges
Recent revisions to the ITRS predict that k values of 3.0 will extend to 90nm and 65nm device technologies. This more realistic approach is likely to yield chips for the 65nm technology sooner than if new porous low-k materials with k<2.5 were introduced. Developments in technologies such as etch, CMP, and metallization for 90nm and 65nm will simplify the dielectric stack, including the thinning and removal of cap and/or stop layers. This evolutionary approach will contribute to some gains in device performance and will tackle the issue of cost reduction.
Although research has been done on second-generation low-k<2.5 with organic and inorganic dielectrics, the organic SODs have long been perceived as the ideal technique for deposition of porous dielectrics because these films can be engineered at the molecular level. In the last year, however, significant progress has been made to extend CVD technology. The incorporation of low-polarized methyl groups or porogen molecules for nano-scaled porosity has been widely examined as an approach to reduce capacitance. Since these films typically have poor mechanical strength, technology that enhances the mechanical properties, such as e-beam treatment, will likely enable and subsequently differentiate these porous materials. As development of the second-generation low-k material matures, implementation is likely to include many of the initial safeguards used in the early learning of low-k implementation — especially the cap and CMP stop layers. Furthermore, knowledge acquired at the 90nm and 65nm nodes, particularly with respect to the interplay of die and packaging, will become increasingly essential as manufacturers push to incorporate these k<2.5 films at 45nm.
Conclusion
After numerous challenges, the ability to implement low-k dielectrics into high-volume production was shown. After eliminating problems specific to low-k, yield improvement and product performance enhancement rates were equivalent to or better than those seen in conventional technologies.
Acknowledgments
The paper is dedicated in memory of Dian Sugiarto, who was a key contributor to the success of this project. The authors would also like to acknowledge Joerg Hohage, Holger Schuehrer, Frank Feustel, Peter Lee, Paul Fisher, Frank Koestner, and Susan Weiher-Telford for their contribution to this work. AMD, the AMD Arrow Logo, Athlon, Opteron, and combinations thereof, are trademarks of Advanced Micro Devices Inc. Hypertransport is a trademark of the hypertransport consortium. Other product names used in this presentation are for identification purposes only and may be trademarks of their respective companies.
References
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- E. Ogawa, et al., 2002 IEEE IRPS, pp. 312–321.
For more information, contact Hartmut Ruelke at [email protected] or Meggy Gotuaco at [email protected].