Transistor scaling, obstacles, and key potential innovations

01/01/2004

Overview Solid State Technology has been working with the leaders of the various technical working groups of the 2003 International Technology Roadmap for Semiconductors (ITRS) to outline highlights and crucial changes in the new document. A discussion of some of those changes involving process integration, frontend processing, lithography, interconnect, materials, and high aspect ratio inspection is presented here. For a roadmap overview by chairmen Paolo Gargini and Robert Doering, see p. 72.

For leading-edge logic chips, the 2003 edition of the International Technology Roadmap for Semiconductors (ITRS) [1] projects continued rapid scaling in the physical gate length (L_g) and other transistor dimensions. This leads to difficult challenges in transistor optimization that must be addressed over the next decade and beyond. In the ITRS, the Process Integration, Devices, and Structures (PIDS) chapter and the Front End Processes (FEP) chapter deal with these important issues.

Model-based transistor scaling

The scaling approach is model based; simplified transistor models incorporating the key MOSFET physics were developed and embedded in a commercially available spreadsheet. Using the spreadsheet, the key parameters such as gate dielectric equivalent oxide thickness (EOT), threshold voltage (V_t), power supply voltage (V_dd), etc., were varied iteratively until key device targets were satisfied. The parameter characterizing the performance (speed) of the transistor is the "NMOS delay time constant," also called τ, and τ = CV_dd/I_dsat, where C is the total gate capacitance/unit width of an NMOS transistor with gate length L_g and I_dsat is the saturation drive current/unit width of such a transistor. Note that, everything else being equal, to maximize the performance (i.e., to minimize τ), I_dsat should be maximized.

The ITRS projects different transistor scaling scenarios for high-performance and low-power logic. High-performance logic is for high-complexity, high-performance applications, such as MPU chips for desktop PCs and servers, while low-power logic is predominantly for mobile applications. The key device target for high-performance logic is high speed (at the expense of relatively high leakage current). Specifically, the target is to improve the device speed, τ, at the historic rate of approximately 17%/year. In contrast, the key device target for low-power logic is to carry out the scaling so that specific, low levels of source/drain subthreshold leakage current (I_sd,leak) are achieved (at the expense of relatively low speed). For low-power logic, there are two flavors: low operating power (LOP), which is typically for relatively high-speed mobile applications such as notebook computers, where large-capacity batteries are typically used, and low standby power (LSTP), typically for lower-speed consumer applications such as cellphones, where lower-capacity batteries are typically used. Hence, LSTP has the lowest possible I_sd,leak and corresponding low performance, while LOP has somewhat higher I_sd,leak and performance. In order to meet the requirement of low leakage current, the L_g scaling for LSTP logic lags three years behind that of high-performance logic, while the L_g scaling for LOP logic lags two years behind. (The scaling of the other transistor dimensions for low-power logic lags correspondingly behind that of high-performance logic.) As a result of the ITRS scaling, done using the iterative approach discussed previously, the overall performance and I_sd,leak are highest for the high-performance transistors, moderate for the LOP transistors, and lowest for the LSTP transistors. The rate of improvement of τ for high-performance logic is indeed at the targeted 17%/year, while I_sd,leak is almost four orders of magnitude lower for LSTP than for high-performance logic.

An important issue for high-performance logic is static power dissipation because of the high leakage current, particularly as the leakage current increases with scaling. To keep the static power dissipation within tolerable limits, a common approach is to fabricate multiple transistor types on the chip, including the high-performance, low-V_t transistors discussed above, as well as other transistors with higher V_t and higher EOT to reduce the leakage current. High-performance transistors are used in critical paths, and lower-leakage transistors everywhere else. As a result, the overall chip static power dissipation can be notably reduced without significantly impacting chip performance. Circuit and architectural techniques to reduce static power dissipation are also quite important. These include utilization of pass gates or other techniques to power down temporarily unused circuit elements or blocks.

Key challenges and potential solutions

In the previous section, an implicit assumption is that transistors with the required characteristics can be successfully and cost-effectively fabricated for highly scaled technologies through the end of the Roadmap in 2018. The required characteristics include meeting I_sd,leak and transistor performance projections, along with acceptable short-channel effect control, acceptable control of the transistor parameters' statistical variability, acceptable reliability, and others. It turns out that there are numerous difficult challenges in successfully fabricating such transistors as the technology is scaled with succeeding years, and that significant technological innovations (referred to as "potential solutions" in the ITRS) will need to be implemented in relatively rapid succession to deal with them.

Figure 1. Key transistor scaling. (Data from PIDS chapter of 2003 ITRS)Click here to enlarge image

The first challenge is for high-performance logic: with scaling, there is increasing difficulty in increasing the I_dsat as much as required while holding I_sd,leak to acceptable values. The preferred solution is to enhance the mobility beyond that attainable with standard silicon channels. This can be accomplished by utilizing strained silicon channels to enhance the mobility. (One approach is to epitaxially deposit a thin silicon channel on silicon germanium (SiGe) layers, which have been themselves epitaxially deposited on a silicon substrate. The thin silicon channel is strained because of the lattice mismatch between the silicon channel and the underlying SiGe layers; the percentage of germanium in these layers is critical to optimizing the mobility enhancement [2]. Other reported approaches exploit the strain applied due to the STI or to the silicide in the source/drain, or the capability of various thin films to apply strain to the channel [3], all requiring careful optimization.) The PIDS section projects that MOSFETs with strained-silicon enhanced mobility channels will be initially deployed around 2004 with an enhancement factor of 1.3.

Figure 2. For LSTP logic, scaling up of gate-leakage current density limit and of simulated gate leakage due to direct tunneling. (Data from PIDS chapter of 2003 ITRS)Click here to enlarge image

The next challenge is excessive gate-leakage current as EOT is reduced with scaling. The gate leakage is due to direct tunneling of electrons through the gate dielectric, which increases sharply as the gate dielectric thickness (or EOT) is reduced. The maximum allowable gate-leakage current is closely related to I_sd,leak projections. For LSTP logic, Fig. 2 shows the scaling of EOT, the maximum allowable gate-leakage current density (J_g,limit), and the simulated value of the gate-leakage current density (J_g,simulated), assuming the use of the current oxynitride standard for the gate dielectric. For 2006 and beyond, oxynitride gate dielectric is incapable of meeting the maximum gate current limits. The industry is actively pursuing a potential solution that utilizes high-k material [4], with a significantly higher relative dielectric constant k than the 3.9 for silicon dioxide. As a result, for the same EOT, the physical thickness is larger for the high-k dielectric than for silicon dioxide (as well as for oxynitride, whose k is close to 3.9), and the direct tunneling and hence gate-leakage current should be lower for the high-k dielectric. The PIDS section projects that both LSTP and LOP logic will need high-k gate dielectric by 2006, and that high-performance logic, with its larger allowable leakage currents, will need high-k gate dielectric by 2007.

Another key challenge is electrical depletion in the polysilicon gate electrode, which in inversion increases the equivalent electrical oxide thickness, EOT_elec, by 0.3–0.4nm, and hence reduces the attainable value of I_dsat. As the EOT scales with succeeding years, the impact of polysilicon depletion on EOT_elec becomes proportionately greater. For high-performance logic, the ITRS projects that by 2007, when the EOT is 0.9nm, polysilicon depletion needs to be reduced below that attainable with polysilicon electrodes if the performance requirements on I_dsat and τ are to be met. Metal gate electrodes, which have virtually no depletion, are the most likely potential solution, and the industry is actively investigating them [5]. To set V_t to the appropriate value for PMOS, the work function of the metal gate electrode must be near the silicon valence band (similarly to P⁺ doped polysilicon electrodes), while for NMOS the work function must be near the silicon conduction band (similarly to N⁺ polysilicon electrodes). Either different metals with appropriate work function for the PMOSFET and the NMOSFET, respectively, will be utilized or a single metal type that can be tuned to the appropriate work functions by doping or other methods.

Beyond 2007, when L_g for high-performance logic transistors is projected to be 25nm, effective scaling of classical planar bulk MOSFETs is expected to become increasingly challenging, even with utilization of strained silicon channels, high-k gate dielectric, and metal gate electrodes as discussed previously. Achieving adequate control of short-channel effects for such small devices will be especially difficult. Exceedingly high values of channel doping will be needed to control these effects, and this high doping will lead both to reduced mobility and increased junction leakage. Furthermore, the total number of dopants in the channel for such small devices becomes relatively few, which leads to unacceptably large and irreducible statistical variation of V_t.

A potential solution being pursued is utilization of ultrathin body, fully depleted, single-gate SOI MOSFETs. This type of transistor is schematically illustrated in Fig. 3. It has lightly doped channels, and V_t is set by the work function of the (metal) electrode, which needs to be near the silicon midgap for these fully depleted devices. With the ultrathin body, scalability and control of short-channel effects is significantly enhanced. The PIDS section projects that single-gate SOI will be implemented in 2008. Multiple gate MOSFETs, which also have ultrathin, fully depleted bodies, are illustrated in Fig. 3 along with single-gate SOI. These multiple gate devices have a narrow silicon fin with the gate electrode wrapped around two or more of the fin edges, and the current flows along these edges. The scalability of the multiple gate MOSFET, projected to be implemented in 2010, is improved beyond that of the single-gate SOI MOSFET [6, 7].

Figure 3. Schematic illustration of various types of multiple gate MOSFETs. Portions of this figure are from J.T. Park and J.P. Colinge UC-Davis [6]. Copyright 2002 IEEE.Click here to enlarge image

The overall timing of the potential solutions projected in the PIDS section of the 2003 ITRS is shown graphically in Table 1. With the exception of high-k gate dielectric, these potential solutions are expected to be implemented first for high-performance logic, because the scaling of low-power logic lags behind that of high-performance logic. The timing of these solutions is based on the PIDS scaling scenario. Given the large number of parameters such as EOT, V_dd, V_t, etc., that can be scaled, this scaling scenario and the timing of the potential solutions are good guides for the industry, but there will likely be considerable variance to the actual paths taken by different companies.

Summary

Click here to enlarge image

The scaling in the 2003 ITRS is model-based, and is different for high-performance vs. low-power logic. High-performance logic emphasizes high transistor speed at the expense of relatively high leakage currents, while low-power logic emphasizes low leakage current at the expense of speed. Difficult challenges will arise with scaling, and will require numerous key technology innovations for the industry to meet the desired performance and power requirements.

Reading the 2003 ITRS tables

The tables' colored boxes should be interpreted as: white = solution exists; yellow = solution being pursued; striped = interim or workaround solution exists (these are colored orange in SST's article); and red = no known solution. These tables may be slightly truncated from the official versions and are correct as of press time. The complete 2003 ITRS and tables are available for viewing and printing at http://public.itrs.net.

References

1. Semiconductor Industry Association, The International Roadmap for Semiconductors, 2003 edition, International Sematech, Austin, TX: 2003. (This is available for viewing and printing at http://public.itrs.net.
2. J.L. Hoyt et al., "Strained Silicon MOSFET Technology," IEDM, pp. 23–26, 2002.
3. K. Ota et al., "Novel Locally Strained Channel Technique for High Performance 55nm CMOS," IEDM, pp. 27–20, 2002.
4. H.R. Huff et al., "Integration of High-k Gate Stack Systems into Planar CMOS Process Flows," Proceedings of International Workshop on Gate Insulators (IWGI), Tokyo, Japan, November 2001.
5. Q. Lu et al., "Metal Gate Work Function Adjustment for Future CMOS Technology," VLSI Symposium Dig. Of Tech. Papers, pp. 45–46, June 2001.
6. J-T Park and J-P Colinge, "Multiple-Gate SOI MOSFETs: Device Design Constraints," IEEE Trans. Elec. Dev., 49, pp. 2222–2229, 2002.
7. P. M. Zeitzoff et al., "Integrated Circuit Technologies: from Conventional CMOS to the Nanoscale Era," (presented at the Conference on Nano and Giga Challenges in Microelectronics (2002), Moscow, Sept. 10-13, 2002), in Nano and Giga Electronics, (ed. by J. Greer, A. Korkin, and J. Labanoski), Elsevier Press, Amsterdam, 2003.

Peter M. Zeitzoff is a Senior Fellow at International Sematech Inc., 2706 Montopolis Road, Austin, TX 78741; fax 512/356-7640, e-mail [email protected].