New materials and device structures needed for CMOS scaling
01/01/2004
New materials and device structures needed for CMOS scaling
Many of the frontend process challenges identified in the 2003 ITRS relate to the perception that continued CMOS scaling will require the introduction of new materials in the near term (2003–2007) and new device structures in the long term (2008–2018) (see Table 2). These changes are required if the speed and low-voltage performance of n-channel and p-channel MOSFETs are to continue at historical rates. A central CMOS scaling problem is managing the conflicting requirements of reducing dynamic power consumption while at the same time reducing off-state power consumption. One proposed change scenario is the following:
- 2003–2007: Bulk scaling with performance enhancements resulting from the introduction of high-k gate dielectric layers, dual work-function metal gate electrodes (high work-function gate electrodes for PMOS devices and lower work-function for NMOS devices) in combination with the introduction of high-mobility strained silicon channels.
- 2008–2010: The abandonment of bulk CMOS for leading-edge devices with the introduction of planar single gate, fully depleted (also called ultrathin body) devices having elevated source/drain contacts, as well as the related materials or derivates thereof developed for bulk devices.
- 2011–2018: The introduction of fully depleted multiple-gate devices such as FINFET, Tri-gate, etc., which again include materials-related enhancements.
This scenario is one of several that will achieve the targeted performance enhancements; other scenarios are possible. Some chipmakers have suggested the direct transition to fully depleted multiple-gate devices, thereby avoiding the use of planar fully depleted single-gate devices.
 |
In the near-term years, the above material-related enhancements will likely be introduced into a frontend process environment. This environment has become measurably more complex as chip manufacturers seek to enhance chip functionality and limit chip power consumption by resorting to the use of multiple transistor designs having multiple threshold voltages and gate dielectric-layer thicknesses on the same chip.
Difficult frontend challenges
Tough, near-term FEP challenges relate to the introduction of new materials and also include traditional scaling problems linked to control of critical dimension etching, and the production and control of increasingly shallow device structures. Most of these challenges also carry with them metrology needs that are discussed in the 2003 ITRS publication, which can be viewed at http://public.itrs.net. The near-term challenges are:
- The introduction of new-age stack processes and materials. Issues here include the introduction and CMOS integration of high-k gate dielectric materials and strained-silicon channel materials, the continued enhancement of dual-doped polysilicon gate electrode materials, and the introduction and CMOS integration of dual work-function metal gate electrodes.
- The control of gate etches and doping processes to maintain control of scaled physical gate length and effective gate length. Important issues include the gate etch processes needed to achieve a physical gate length that is smaller than the printed feature size yielded by lithography. There are several critical problems here for existing gate stack materials, and these problems will be made even more difficult with the introduction of new materials.
- The management and control of interface structure, composition, and elimination of interface contamination. Issues here relate to near-term pre-gate surface preparation challenges for scaled silicon oxynitride gate-dielectric materials, as well as those linked to the introduction of high-k gate dielectric layers and dual metal gates. Here the challenge is not only the control of interface contamination, but also the achievement of a dielectric/silicon interface that is controlled in its structure and chemical make-up. In addition, the need for continuous reduction in particle surface contamination in progressively more shallow and fragile device structures will offer difficulties.
- Processes for scaled MOSFET dopant introduction and control. Key issues here are dopant introduction and activation processes related to the minimization of source/drain parasitic resistances and parasitic capacitances. The parasitics must be minimized in order to achieve acceptable scaled MOSFET drive currents for both bulk and fully depleted devices.
- Introduction and CMOS introduction of new memory materials and processes. Although not covered further in this article, scaled DRAM and flash memory devices require the introduction of new dielectric layer materials, and for DRAM the introduction of new electrode materials. The DRAM requirements are driven by the need to maintain storage capacitance despite a continuous reduction in bit storage area.
The long-term difficult challenges are similar to the near term, with some notable new ones linked to the introduction of new device structures such as FinFET and its derivatives, as well as the introduction of new memory devices. One additional and important issue identified in the long term is the need for the next-generation starting substrate material, which is anticipated in the year 2011. There is some question that current wafermaking processes can be cost-effectively scaled to the next larger wafer size, which probably will be 450mm.
Frontend surface preparation
While some aspects of the frontend surface preparation roadmap have remained the same since 2001, there are several changes.
 Figure 4. Frontend technology nodes and the years during which research and development and qualification/preproduction will take place. |
Particle specifications need to be considered not only with respect to pre-gate oxidation cleaning, but also to post-ash cleaning after gate electrode formation. Generally, since the start of production of the 0.25µm technology node, megasonics energy has not been used for cleaning with the gate structure in place to avoid physical damage to the gate structure. Particle removal efficiency was maintained in these cleaning steps by using processes that etch a considerable amount of surface material, undercutting the particles to release them from the surface. However, increased integration of transistors with different threshold voltages on a single chip has led to an ever-increasing number of implant masks, which results in excessive removal of surface oxide and silicon during cumulative post-ash cleaning steps. The surface preparation roadmap now specifies the maximum allowable loss of oxide and silicon during each cleaning step. Tightening of this specification and the current inability to use megasonics will make it difficult to achieve front surface particle specifications in the near future. This is indicated by the yellow coloring for front surface particles in 2006 and for silicon and oxide loss in 2005. In 2008, we are concerned that current cleaning processes will not be able to achieve sufficient particle removal while removing less than 0.4Å of surface material. The potential solutions chart (Fig. 4) indicates that this challenge may be met soon by new megasonics or aerosol techniques, and possibly in the future by the use of advanced surfactants and supercritical CO2 technologies.
Metrics for surface contaminants such as metals, mobile ions, carbon, and oxygen remain essentially the same as with the past roadmap; however, it is unclear if the introduction of high-k gate dielectrics and SOI substrates will change the sensitivity of device performance to these contaminants. More studies of the effect of these contaminants need to be carried out with new materials and substrates.
High-k gate dielectrics introduce new challenges in surface preparation. It appears that a controlled, ultrathin oxygen-passivated surface may be most desirable before dielectric deposition. Another challenge is removing the high-k dielectric from source and drain areas after gate formation. The high-k materials under consideration, such as hafnium oxide, are very resistant to common chemicals currently used in wet etching processes, but they must be removed without excessively etching isolation oxide, the gate electrode, or the underlying silicon. The addition of metal-gate electrode materials will make this removal step even more challenging.
One more aspect of the 2003 surface preparation metrics to note is with respect to back surface particles. The values for this metric have been removed in 2003 because the model being used in 2001 could not be adequately verified or validated. It will be a focus of the 2004 update to determine meaningful metrics for back surface particles with a model that has a direct correlation to device yield.
Critical dimension etching
The most difficult frontend etching process is gate etch. The MOSFET gate length represents the smallest etched feature, yet it requires the greatest dimensional control.
The historical expectation for gate length control has been 10% 3σ inclusive of random variance contributions, from both the lithographic and etching processes. In the prior and current roadmaps, the variance (σ2) contributions from the lithographic and etch processes were assumed to be statistically independent, implying that their respective variance contributions are additive. It is noted that this assumption neglects any added variance contribution from interactive terms that may arise out of statistical interdependence. Therefore, the etch variability requirement values should be interpreted to mean the least allowable.
Within this framework of statistical independence, the variance contributions were apportioned between lithography and etch based on process modeling. For the 2001 ITRS, the total allowed gate length variance (σ2) was apportioned 67%/33% between lithography and etch, respectively. With the 2003 ITRS, the variance was apportioned 80%/20%, resulting in more stringent etch control requirements.
Achieving this degree of control is made more difficult by current industry practice that employs a resist trim process to reduce the lateral feature size of the resist, before etching the pattern into the polysilicon gate material. The allowed etch variance contribution was apportioned between resist trim and etch, again assuming statistical independence. This is reasonable if the printed features have vertical walls, and so long as the resist trimming process does not excessively reduce the resist thickness.
 |
Another important etch challenge is the requirement that the gate etch process terminate on the very thin gate dielectric without damage to the gate dielectric layer and punch-through into the underlying device channel edge. Such punch-through would result in thinning of the device source and drain extensions, which are very shallow, highly doped regions that represent an important part of the overall source/drain parasitic resistance.
Finally, it is noted that these requirements must be maintained despite the introduction of new high-k gate dielectric layers, and dual work-function metal-gate electrode materials.
The 2003 ITRS etch requirements are summarized in Table 3. It is noted that there are some very near-term red walls. In addition, the cross-hatched cells indicate that these requirements cannot be achieved, but the workarounds are currently in use to mitigate the failure to meet the requirements. The 10% 3σ requirement for gate length control is currently under review as part of the 2004 ITRS update. This represents an ongoing challenge, and many device manufacturers are beginning to employ designs to accommodate greater gate-length variability.
Thermal and thin films
While the 2001 ITRS primarily reflected bulk CMOS processing, the 2003 roadmap reflects both new materials and new devices for frontend processing. As discussed in the introduction, CMOS devices made on bulk silicon will soon require both high-k dielectrics and metal-gate electrodes; after 2007, single-gate and dual-gate SOI will be needed for evolution beyond bulk CMOS.
In the area of thermal and thin films, one of the most difficult challenges for future device scaling revolves around the growth or deposition of reliable, ultrathin (with electrical equivalent thickness ≤1.0nm) gate dielectric layers, and the development of depletion-free, low-resistivity gate electrode materials. Requirements for the equivalent oxide thickness (EOT) of high-performance devices are illustrated in Fig. 5. Figure 5 also shows that gate dielectrics as thin as 1.3nm (oxide equivalent) are in production today. However, even with oxynitride dielectrics, direct tunneling currents through the gate stack are projected to exceed the ITRS requirements — first for low-power devices in 2006 and then for high-performance ones in 2007, as shown in Fig. 6.
A significant global research and development effort has been implemented to identify and qualify a suitable alternative gate dielectric material. The Hf-based family of high-k gate dielectrics, particularly nitrided silicates, has been significantly studied during the past several years, and some very encouraging results have been reported. However, notwithstanding a couple of highly visible announcements about the incorporation of high-k materials in future products, serious technical issues still exist, including charge trapping, channel mobility, Fermi-level pinning of gates, and long-term reliability.
Scaling the EOT below about 0.8nm is expected to require the identification of materials with even lower tunneling leakage (higher k and/or band offsets) and stability, interface-state densities, and reliability approaching that of high-quality gate SiO2. Current approaches employ a thin SiO2 layer to preserve interface-state characteristics and channel mobility. This interface layer adds appreciably to the equivalent oxide thickness, mitigating any benefits that accrue from the use of the high-k dielectric. Even the presence of an intermediate layer of O-Si-O bonding to bridge between the silicon substrate and high-k metal ions is expected to limit the scaling of equivalent oxide thickness to nominally 0.4nm. Accordingly, the 2003 roadmap reflects EOTs that asymptote to 0.4nm rather than to 0 (see Fig. 5).
The gate electrode comprises the second part of the challenge in gate stacks. Metal-gate electrodes are needed to eliminate poly-Si depletion effects that can add several tenths of a nanometer to the electrical oxide thickness. Bulk devices require two gate materials: one having a Fermi level near the Si conduction band (for NMOS devices) and one near the valence band (for PMOS devices). Adding to this challenge is the problem of integrating a metal-gate process into a conventional CMOS process flow. First of all, the metal gate must be thermally stable during junction-annealing thermal cycles. And the environmental sensitivity of the leading high-k dielectric candidates precludes the use of two separate metal deposition steps; thus, considerable research is focused on metal systems whose work functions can be tuned over a wide range by (locally) varying their composition. The introduction of single-gate, fully depleted, ultrathin-body SOI devices with intrinsic channels will change the optimal values of the gate work functions to near mid-gap, further emphasizing the need for tunable work-function systems.
In order to maintain high-device drive currents, technology improvements are required to increase channel mobility of traditional bulk CMOS devices, as well as in partially and fully depleted SOI devices. The use of strained channel layers, such as strained Si on relaxed SiGe for NMOS and strained Si on strained SiGe for PMOS will help in achieving this objective but will require considerable process optimization. These enhanced mobility (e.g., strained) channel devices may be needed in conjunction with oxynitride gate dielectrics, before the introduction of high-k materials. Alternate devices such as nonstandard, double-gate devices anticipated in the longer term also require high-mobility strained silicon channels.
Even with the successful introduction of these new gate stack materials, the limitations of planar bulk CMOS transistors, particularly increased subthreshold leakage currents exhibited at reduced threshold and drive voltages, will drive the introduction of new device structures such as fully depleted, single-, and multiple-gate transistors. This rapid introduction of new materials and device structures in the next five to seven years constitutes an unprecedented multiplicity of challenges to develop and integrate these developments into effective, cost-efficient production technologies.
Sidewall spacers currently are used to achieve isolation between the gate and source/drain regions, as well as to facilitate the fabrication of self-aligned, source/drain-engineered dopant structures. The sidewall spacer's robustness limits the gate and source/drain contacting structure and the processes that can be used to form these contacts. Sidewall spacers traditionally have been formed from deposited oxides, thermal oxidation of polysilicon, deposited nitrides, and various combinations thereof. Traditional sidewall processes will continue to be used at least until the time (about 2008) when elevated or raised source/drain structures are required, at which time process compatibility with the sidewall spacer will become critical. Fully depleted SOI devices will require thin, robust sidewalls having gate dielectric-like reliability and stability. They must also be optimized to minimize parasitic capacitance and series resistance. Below ~10nm, even the best state-of the-art spacers are susceptible to defect formation when subjected to selective epitaxial silicon or silicide processes anticipated for elevated contact structures. More research is needed to find and qualify an acceptable sidewall spacer compatible with the high-k gate dielectric.
 Figure 7. (left) Shallow-trench isolation aspect ratio and sidewall angle requirements for bulk CMOS. Figure 8. (right) Shallow-trench isolation parameters. |
The 2003 roadmap also outlines the issues for shallow trench isolation, where decreasing trench width and higher aspect-ratio gaps require controlled uniform filling of dense/isolated structures (see Fig. 7). In the fabrication of shallow trench isolation structures, the top corner of the active region is generally exposed by HF etching of pad and sacrificial oxides prior to the growth or deposition of the gate dielectric. The gate conforms to this corner, forming a region of higher electric field and potentially high defectivity. This region can be thought of as a lower-threshold-voltage transistor in parallel with the bulk transistor, leading to a 'hump' in the Id/Vg characteristic and higher subthreshold leakage. Accordingly, the top corner of the STI trench is rounded (Fig. 8), usually by oxidation prior to the deposition of the isolation oxide. Increasing the radius of curvature of this corner increases the Vt of the parasitic transistor and decreases the magnitude of this hump. Unless new processes are used, however, device scaling will lead to a decreased radius of curvature.
The magnitude of the parasitic drain current also depends on the degree of recession of the field oxide adjacent the active edge (Fig. 8) since that will in part determine the cross-section of the edge 'transistor.' Thus, as the radius of curvature is scaled down with the isolation width, hopefully the recession of the field oxide is as well, resulting in at least partial mitigation of the degradation associated with the decrease of the radius of curvature. This oxide recession depends on the 'hardness' of the deposited isolation oxide to CMP processing and to HF dipping, and to the thickness of the pad and sacrificial oxides, all of which are process design choices optimized at each technology node.
Doping and contact formation
Table 4 shows requirements related to doping for contact formation. The most significant change in the 2003 ITRS is that there are longer "red brick walls" in the requirements for maximum drain-extension sheet resistance and drain-extension lateral abruptness. There are several reasons for this, but primarily, there is the big picture realization that traditional scaling of bulk CMOS devices is becoming increasingly unworkable and that new materials and device structures will have to be introduced within the next 10 years. Consequently, for the years 2008 and beyond where fully depleted devices are expected, the drain-extension junction depths become easily achievable since they are limited and defined by the physical thickness of the channel (which itself follows a scaling rule). In the near term (2003–2007), the junction depths still decrease rather aggressively, from 24.8 to 13.8nm (±25%). While such values have been demonstrated in research and development using ion implantation and a variety of annealing schemes, including solid-phase epitaxial regrowth, laser spike annealing, or flash-assist arc lamp annealing [1], these have not yet been demonstrated in manufacturing. The reason for not color-coding these requirements is that the models available to predict the requirements for junction depth and sheet resistance are quite crude and not sufficiently accurate to define requirements. For these reasons, the model outputs for these items are listed as targets, not as requirements. (See footnote [K] of Table 59a of the 2003 ITRS FEP chapter.)
 |
While the lateral abruptness requirements remain as aggressive as in the 2002 update, targets are now set only as far out as 2007, since the device structures are expected to change at that time (see Table 4) and the modeling is not yet available. (For a more thorough discussion of the lateral abruptness requirement in the 2003 edition, see both the footnotes to Table 51a in the ITRS document and the section titled "Source and Drain Extensions" — it makes clear that the relationship between increasing abruptness and a gain in on-current is not straightforward.) While increasing lateral abruptness reduces the accumulation resistance of the drain extension, it also influences the spreading resistance. Modeling shows that a too steep lateral junction can even degrade a device's short channel behavior.
Contact silicide and metal gate
In the near term, to 2007, Table 5 shows that NiSi adoption is expected to enable the simultaneous achievement of targets for the contact Xj, maximum silicon consumption, and contact silicide sheet Rs. In the longer term, a manufacturable and CMOS integrable solution consisting of selective deposition of silicon epitaxial layers, to provide enough silicon to be consumed to form a continuous silicide, is still being sought. The contact resistivity, however, is still a challenge with the 2004–2007 targets shown as yellow and beyond that in red. The contact size assumption (contact length = 2 × MPU pitch) made to arrive at the target values is spelled out in the ITRS document, and stresses that for real devices the contact resistivity, drain extension Rs, and lateral abruptness need to be co-optimized to meet the overall parasitic resistance requirements. The adoption of epitaxially deposited SiGe, because of its lower barrier height, could address both the contact resistivity and maximum silicide consumption issues.
 |
In recent months, NiSi has also become identified as a leading candidate material for forming metal gates [2]. It has been found that dopant implantation into the poly prior to fully siliciding the poly can allow achievement of dual work functions that are compatible with n- and p-type MOSFETs.
Doping potential solutions
Figure 30 in the 2003 ITRS (not shown) summarizes some doping potential solutions. Changes from the 2001 ITRS are notable. Conventional low-energy (beamline) ion implantation, the incumbent dopant introduction technology, appears as the viable solution for USJ ion doping out to the roadmap's end (2018 in this edition). The development period for plasma doping has been extended to 2007. For USJ doping activation, the ~1 sec-type spike anneals are expected to be replaced in the next few years by msec duration anneals (flash or nonmelt laser) and/or solid-phase epitaxial regrowth. While the latter is appealing because it does not require any added equipment development, significant challenges remain, such as unannealed damage to gate sidewall or gate dielectric edge [1]. Either way, the next-generation dopant activation solution is expected to enter preproduction in 2007. The recognition of significant integration issues has pushed out the development period for melt laser solutions to 2013.
Conclusion
Continued transistor scaling is causing incumbent frontend materials to approach fundamental physical limits. Thus, scaling is limited not only by the ability to lithographically produce small features in resist, but by the introduction of new materials and device structures that will support the enhanced performance expected of scaled p-channel and n-channel MOSFETs. Solutions to the many materials problems identified, their introduction, and CMOS integration pose significant challenges that will permeate virtually all aspects of frontend processing.
References
- R. Lindsay, B.J. Pawlak, P. Stolk, and K. Maex, "Optimization of Junctions Formed by Solid Phase Epitaxial Regrowth for Sub-70nm CMOS," MRS Proc., 717, 2002.
- J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, et al., "Metal-gate FinFET and Fully-depleted SOI Devices Using Total Gate Silicidation," IEDM Tech. Dig., 247, 2002.
Walter Class is strategic marketing director at Axcelis Technologies, Beverly, MA; ph 978/787-4000, e-mail [email protected].
Michael Jackson is IBM account executive, formerly director of frontend processes, at International Sematech Inc.
Additional authors are: Jeff Butterbaugh (Surface Preparation section), Carlton Osborn (Thermal Films section), and Aditya Agarwal (Doping and Contact section).