Will new technical solutions help lithographers in the future?
01/01/2004
Comparing the new 2003 edition of ITRS Lithography Chapter with the year 2002 Update, it becomes apparent that the largest differences are related to the narrowing of potential solutions for near-term nodes and to the introduction of novel techniques for mid- and long-term nodes. The main purpose of these further options is to guarantee device geometrical specifications on time; additionally, extending the lifetime of already used and known techniques is also predicted.
The choice for the 90nm half-pitch node, forecast in 2004, is a 193nm scanner with "hard" resolution enhancement technology (RET) and phase shifting on the most critical layers. Looking at the future, so-called "immersion" lithography, in which the volume between the wafer and the scanner objective lens is filled with a liquid (e.g., deionized water in the case of 193nm wavelength), looks like a promising technique. Immersion allows a larger NA and thus better ultimate resolution without exchanging the overall manufacturing infrastructure in the cleanroom. Its feasibility for the 65nm node will be assessed by the middle of next year. Immersion might also enable safe wafer processing for the 45nm node, where EUVL technology might otherwise first be used.
Another option for later nodes is "imprinting" lithography, in which a template is used to mold the resist. "Maskless" lithography is also an option, provided that sufficient tool throughput is reached and that overlay with layers processed by optical tools can be maintained within specifications.
The main aspect driving the final choice among the technology options at each node will be the degree of maturity at the first node where this technique happens. Performance must meet the requirements for the node as well as or better than other options, and the technology must be cost-effective.
The great challenges lithographers have to face in the coming years are the printing of gates for microprocessors and of contact holes with the proper degree of CD and overlay control. The former parameter has in fact a heavy impact on microprocessor clock frequency, while both account for the device yield.
Despite the fact that for the very first time since the ITRS was introduced no further acceleration in node timing has been applied from the prior update, and that a larger CD budget was assigned to the lithography process step, CD control for gate is still the most critical parameter for lithography and drives the first red bricks in the lithography tables. This aspect is even more dramatic than before, for several effects that were usually negligible in the past become more and more important when printing structures in the sub-100nm range.
For the 90nm and 65nm nodes, and quite possibly the 45nm node, lithographers are likely to choose optical solutions. For this approach, the two largest contributors to gate CD variation are reticle CD control and linearity (especially for processes requiring binary masks, because of the high inherent mask-error factors — MEF) and scanner-lens focus control and aberrations. These last error contributors become most significant whenever hard OPC strategies are required with extreme off-axis illumination. On the other hand, the adoption of alternating phase-shift masks lowers the MEF but demands extra effort from maskmakers due to the higher complexity of their production process.
 Figure 9. Gate CD distribution for 90nm node (best case). |
Another important source of gate CD variation is the roughness of the resist profile, which can be as large as the required overall control budget; a thorough definition of this key parameter, previously unavailable, has been established in order to complete the model of gate CD distribution introduced last year. The previous model accounted for intrafield, interfield, and wafer-to-wafer variations.
Results of simulations performed by Sergei Postnikov and Scott Hector of Motorola for the most promising process involving alternating phase-shift masks are shown in Fig. 9. This figure shows CD variation for different methods of summing error sources and for three different gate pitches (240nm, 360nm, and isolated). These simulations clearly showed that for near-term nodes, ±10% of final MPU gate dimensions cannot be achieved with any known combination of technology and process. There are alternatives, such as microprocessor layouts, that restrict the number of pitches for gates or designs, and transistors that are inherently more tolerant of CD variation.
These options will be the subjects of future discussions among various ITRS working groups. Lithographers must continue to focus on the sources of CD variation, such as reticles, focus control, and resist line-edge roughness, to improve linewidth control over time.
Mauro Vasconi can be reached at e-mail [email protected]; Scott Hector at [email protected]; and Harry J. Levinson at [email protected].