New ITRS targets k values, structures, and global wiring
01/01/2004
The 2003 edition of the International Technology Roadmap for Semiconductors (ITRS) continues to reflect a slower-than-projected rate of reduction in effective k value for MPUs and ASICs. Although materials manufacturers have been able to introduce materials with the necessary bulk k value, other properties have created integration challenges for the typical device structure, as shown in Figure 10. Reducing the effective k value is still considered a key goal.
 Figure 10. Typical CMOS device cross-section. |
The problem of rising conductor resistivity, highlighted in the 2001 ITRS, is a near-term issue, with performance impacts expected for the 65nm technology node. For the long term, material innovation with traditional scaling will no longer satisfy performance requirements. Radical solutions to the interconnect problem, now in research stages, will need a strong focus if they are to be brought to production soon. Two other issues that will require a break in the 40-plus years of interconnect technology — engineering manufacturable interconnect structures with new materials and processes, and identifying solutions that address global wiring scaling issues — round out the top three difficult challenges in interconnect technology.
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The dielectric constant targets are again being relaxed (see near-term changes in Table 6), reflecting the difficulty in achieving a solution that combines electrical reliability, manufacturable materials, and an effective manufacturing process. The effective dielectric constant is now model-based. The model delivers expected dielectric constant based on the thickness of the bulk film; presence, thickness, and k value of any dielectric barrier and masking films; and an estimate of the capacitance effects of etch- or clean-related dielectric sidewall damage. The output — a range of effective dielectric constant values — is a more realistic reflection of the integrated structure.
Bulk low-k material choices are narrowing to a few formulations. These materials in their "dense" form reach dielectric constant of approximately 2.7. To achieve lower k values, density must be reduced by creating porous structures. This has widened the window of opportunity for CVD providers to meet roadmap targets. The low-k bulk materials all have structural and chemical resistance properties that generally are orders of magnitude poorer than SiO2, FSG, or doped glasses. Only limited improvements in the materials' bulk mechanical properties are expected, and these are exacerbated by porosity. The low-k solution will therefore involve not just finding the right bulk material but developing an entire system of materials, processes, and designs that work in concert to keep the capacitance of the overall interconnect structure low. Though starting with a markedly weaker material, this solution must provide an electrically and mechanically reliable structure. Typical low-k integration schemes are shown in Fig. 11.
With cleaning steps representing as much as one quarter of an advanced process-flow step count, the interconnect chapter has an expanded section on surface preparation, including a technology requirements table and associated potential solutions (http://public.itrs.net). Approaches are discussed, such as cleaning with dense fluids or supercritical CO2, combined with solvents and surfactants. Alternative hydrogen-reducing gas chemistries might be needed for stripping photoresist from porous silicon oxide or similar low-k materials. Promising hybrid approaches will combine multiple technologies in gas and liquid phases to meet surface preparation, cleaning, and stripping requirements.
The chief metallization challenges will be to provide very thin barriers and nucleation layers. The single-digit nanometer thicknesses are best addressed by atomic layer deposition (ALD) or its variants, which are excellent processes for meeting both co-formality and thickness control, for deposition of barriers and nucleation layers, as well as high-k dielectrics. Although the roadmap does not predict an alternative to electrochemical deposition for bulk Cu fill, there is a need for an alternative to PVD technology, such as electroless deposition or 'seedless,' or even self-nucleating layer barriers (conductor potential solutions). Porous dielectrics add further challenges; it is well known that CVD and/or ALD precursors penetrate the pores, and methods to seal or temporarily stuff them during barrier deposition are needed.
Doped Cu also has emerged as a potential solution for improved Cu reliability, but this solution needs to be balanced against the increased resistivity that occurs. Increases in Cu line resistivity due to electron scattering from the line top, bottom, and sidewalls already are evident in the finest wiring, and are expected to first limit conductor performance at intermediate wiring levels. Ironically, this effect occurs earlier in Cu than the other common metal conductors, Al, or even W. Efforts in pattern transfer to provide smooth walls permit the 'best case,' pure specular reflection of electrons, but atomic-level smoothness must be obtained.
CMP remains the leading planarization technology in current and future manufacturing. Alternative conductor planarization techniques that eliminate shear stress on the Cu, for instance, chemically enhanced planarization (CEP) and spin-etch planarization (SEP), use chemical or electrochemical means to remove metals. These alternatives must still achieve the same planarization capability of CMP, and the 2003 ITRS describes new dishing-erosion-thinning metrics for planarization.
No 'new' etch source technology is anticipated, for either low-k dual-damascene or high-k materials etches. Deep contacts and backside via holes may use new gases, including xenon-containing mixtures. The biggest challenge will be greater control of etch to ensure pattern fidelity, with a multiplicity of levels combined with new materials, reduced feature size, and pattern-dependent processes, in all three dimensions. In fact, three-dimensional process control of critical dimensions (3DCD), with its associated metrology, is necessary for IC performance and reliability. The dominant damascene architecture requires tight control of pattern transfer, etching, and planarization. High-k materials and capacitor electrodes, which might contain compounds such as barium strontium titanate or metals including ruthenium, have their own unique set of issues and new etch chemistries, and they will need to be developed. Since many of these materials have low-volatility species, a high degree of bombardment is required during etching, yet this must not induce device damage. Shorter-wavelength and/or higher-resolution resists continue to exhibit less etch resistance, placing a greater burden on selectivity. Consequently, the industry will probably make greater use of sacrificial layers such as hard masks and/or BARCs.
To extract maximum performance, interconnect structures cannot tolerate variability in profiles without producing undesirable RC degradation. It is desirable to remove the intermediate etch stop between the via and line levels of the dual damascene structure to lower the overall effective dielectric constant. This requires profile and rate control at the bottom as well as the sides of the etch front. Dimensional control will become even more critical as new materials, such as porous low-k dielectrics with weaker mechanical properties, play a role.
New interconnect concepts
Within the next 10 years, innovation in conventional materials combined with traditional scaling will no longer satisfy IC interconnect performance requirements. Equivalent scaling and more radical solutions are foreseen; these may involve different signaling means, such as optical or RF, or the use of nanostructured materials with exotic mechanical or conduction properties.
The most promising near-term solution anticipated for the global interconnect problem is design modifications to minimize global wiring lengths. One option is to move some interconnects from the primary chip to thicker metallization with higher performance on the package or on a supplementary chip designed to carry only interconnects. These signals would then be transferred back to the primary chip. In some cases, a "sea of leads" approach might be used to provide substantial density increases in I/O, benefiting both global interconnect and power and ground connections. A more aggressive approach is the fabrication of 3D ICs, where active device layers would be stacked among intervening layers of interconnects. Various schemes can be employed to fabricate these from simple stacked die, in use today, to elegant low-temperature fabrication of transistors in the interconnect layers.
Beyond wire length reduction, there are more radical alternatives to the usual metal-dielectric interconnect options. One is to use electromagnetic transmission of signals from one part of a chip to another. This option takes the form of a "LAN on a chip" with transmitters and receivers combining antennas and appropriate signal-generation and signal-detection circuitry. Optical interconnects also are being considered an option for replacing the conductor-dielectric system for global interconnects. The optical approach has many variants, the simplest perhaps having emitters off-chip and only free-space waveguides and detectors on-chip, with progressively more complex options culminating in complete monolithic emitters, waveguides, and detectors.
The most radical options for global wiring solutions include nanotubes, spin coupling, and molecular interconnects. Recent measurements have shown that nanotubes can have very high conductivity based on ballistic transport and can be grown at designated locations and interconnected from site to site.
Many of these options have common challenges. The optical solution and many of the RF solutions require the incorporation of low-power, low-latency components that now exist only in compound semiconductor form, usually involving tens of heteroepitaxial layers. A means to either make or integrate these devices onto silicon, or a means to achieve their function in silicon, must be found.
These alternative signaling technologies (3D, RF, optical, nanotechnology) will compete with Si CMOS enhancements that continue to provide the performance, functionality, and cost targets of the overall roadmap. Chip designers, in the absence of proven options, add more wiring layers without fundamental changes to the base fabrication technology. This has allowed the MPU community to achieve a doubling in effective performance every 2.5–3 years without more aggressive interlevel dielectric constants. Ultimately, interconnect innovation with optical, RF, or vertical integration combined with accelerated efforts in design and packaging will deliver the solution. It has been difficult for the community to define an unequivocal physical or technical end to this paradigm.
Christopher Case is the ITRS' Interconnect Technical Working Group chair, and CTO at BOC Edwards, Murray Hill, NJ; e-mail [email protected].