International Sematech tackles emerging materials

01/01/2004

Emerging materials will augment silicon transistor technology by providing enhanced speed, lower power consumption, improved heat dissipation, or added RF/analog functionality while maintaining the large-scale integration capability of CMOS technology. Alternative materials implementation, in conjunction with traditional CMOS scaling, is considered essential for maintaining CMOS technology roadmap targets, thus the 2003 ITRS Starting Materials sub-Technical Working Group established a team focused on addressing alternative substrates, or emerging materials — the Emerging Materials Team.

The team's objective is to provide guidance for the industry regarding novel starting materials structures and processing methodologies that will enhance silicon-based CMOS technology, allowing it to meet anticipated roadmap scaling requirements. The augmentation of the silicon starting material need not be entirely silicon-based as long as CMOS improvement is the end goal. As an example, the integration of III-V compound optoelectronics on Si for enhanced bandwidth for I/O limited CMOS technologies would be considered a topic for the team, but the fabrication of III-V on Si devices for discrete implementation without any incorporation of a Si microelectronics theme would not.

For the 2003 ITRS, the team has identified the following emerging materials that will be tracked going forward: 1) strained silicon and its embodiments, 2) Ge MOSFET structures, 3) high-resistivity silicon, 4) isotopically pure silicon, and 5) integrated optoelectronics on silicon.

Forward-looking development approaches may differ. Where possible, the committee has strived to present general embodiments of the five identified issues; however, where appropriate, more established approaches are highlighted. In addition, questions are raised if the long-term cost-effectiveness or technical merits of an approach are not clear.

Strained silicon and its embodiments

Modern transistor technology is approaching the limit of the fundamental electronic capabilities of Si. High-mobility materials for enhanced transistor speed and reduced power consumption are considered paramount for advanced CMOS applications. Strained Si technology — the introduction of elastic strain in Si transistor architectures via wafer-scale epitaxial processing — is the most well-researched and widely accepted method for enhancing the carrier mobility in Si. However, it should be noted that techniques to generate local strain in silicon via transistor processes (e.g., isolation, source-drain contact technology, etc.) are also being investigated by various manufacturers.

Key parameters and associated ranges of values, which should be considered at the time that strained Si target specifications are more narrowly defined for the ITRS, are discussed below. There are five strained Si embodiments that are addressed:

• Bulk strained Si. The analog of today's Si CMOS p^-/p⁺ epi substrates comprise an epitaxial strained Si film on top of a uniform-content SiGe layer, whose lattice constant is engineered by a compositionally graded SiGe layer.
• Strained Si on SiGe-on-insulator (SGOI). The merging of strained Si technology and silicon-on-insulator (SOI) technology entails a strained silicon film on top of a strain-generating, uniform-content SiGe layer, with an insulating layer residing below it. As with conventional SOI, the SGOI substrate structure can be tailored for partially depleted (PD) and fully depleted (FD) application.
• Strained Si-on-insulator (SSOI). This is the merger of strained Si and SOI technologies with the exclusion of a SiGe layer for strain generation. As with SGOI, SSOI can take on PD and FD embodiments.

For the purpose of this section, the targets are being constrained by two criteria: 1) The strained Si film is fully strained in all circumstances (i.e., misfit dislocation formation is not favorable under any circumstance); and 2) The SiGe below the strained Si film is 100% relaxed.

Note that these constraints need not be necessary for strained Si wafer and transistor fabrication, but facilitate a useful starting point for tracking the embodiments of strained Si technology.

Table 7 lists the key parameters to be examined when establishing target specifications for strained Si and the associated ranges that are likely for the earliest embodiments. In addition, methods for measuring strained Si substrate characteristics are tabulated: spectroscopic ellipsometry (SE), x-ray diffraction (XRD), etch pit density (EPD), plan-view transmission electron microscopy (PVTEM), atomic force microscopy (AFM), and optical interferometry. It is important to note that the tabulated metrology methods represent the current state-of-the-art in research and development applications, but some of the techniques will probably be replaced with more production-friendly, nondestructive techniques.

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All substrate specifications not mentioned in Table 7 (e.g., wafer site flatness, warp, etc.) should comply with typical epitaxial wafer guidelines.

Methodology for target values

It was assumed for the table that PDSOI would implement a starting film thickness between 500Å and 800Å. FDSOI starting film thickness was specified as being between 150Å and 500Å. For the sake of this document, the underlying insulator thickness was considered independent of any strained Si parameters, so it is not tabulated as a separate variable.

The strained Si thickness range was set in all cases, except for that of SSOI, at the limits of critical thickness as defined by the Matthews-Blakeslee criterion, which establishes the thickness limit beyond which the onset of misfit dislocation formation is favorable [1]. The values in the table allow some additional margin to account for the fact that although the Matthews-Blakeslee criterion is based upon a verified model, thin-film mechanical properties and other factors, which are difficult to measure, do not allow an exact determination of the critical thickness. It should be stated that the Matthews-Blakeslee criterion is an equilibrium criterion and that, by definition, the thin film is stable at all temperatures. It is a common misconception that strained Si films will relax upon thermal processing, when in fact, this will only occur if the film was beyond the critical thickness to begin with and in a metastable state.

In the case of SSOI, the strained Si thickness limitations are more complex and not completely understood at this time [2]. The SSOI fabrication process plays a significant role in determining the interfacial bond strength and integrity between the strained Si film and buried insulator layer, influencing the volumetric strain limits for an SSOI structure.

The Ge content range was selected based upon the research and development results with bulk strained Si transistors, which have largely centered in the 15%–30% Ge range. In this range of Ge content, or corresponding strain content, listed in the adjacent column in Table 7, the electron mobility enhancement has generally been reported to be 60%–100%, while the hole-mobility enhancement has been reported to be in the vicinity of 5%–60%. The SiGe layer thickness range is constrained only in the case of the PD and FD structures (as noted above) with a SGOI configuration. The upper limit of SiGe layer thickness was calculated by subtracting the minimum strained Si thickness values from maximum allotted total PD and FD film-thickness approximations (e.g., in the case of PD SGOI, the largest SiGe thickness attainable would be 800Å-75Å). The lower limit was calculated by subtracting the maximum strained Si thickness from the minimum allotted total PD and FD film-thickness approximations.

Threading dislocation density is controlled by the kinetics of dislocation introduction in SiGe graded layers. State-of-the-art results show dislocation densities <10⁵/cm², but commercial efforts are generally focused in the range <5×10⁵/cm². In addition to the overall threading dislocation density, the local concentration of dislocations in threading dislocation pileups or entanglements needs to be tabulated by measuring their total length and dividing by the viewable area.

The metrology techniques listed to measure both forms of defects are EPD and PVTEM. It is important to consider that at very low dislocation density (10⁶/cm²), PVTEM techniques should always be used to verify the counts determined by EPD.

Short-range surface roughness is measured on a 1µm × 1µm scale while long-range surface roughness is measured on a 40µm × 40µm scale. Both measurements are necessary because the short scale roughness could affect transistor performance, while the long-scale roughness measurement is needed to ensure adequate topography for lithographic patterning techniques. In addition, roughness at both levels retards the effectiveness of metrology techniques that rely on light-scattering measurements (e.g., light point defect and haze measurement methods).

Ge MOSFET structures

The overwhelming dominance of silicon as an electronic material is largely based on the synergy between the silicon itself and its thermal oxide, SiO₂. For decades, thermal SiO₂ has provided the best possible surface passivation and it is a superb gate insulator. However, as the industry is considering a transition to a non-SiO₂ gate insulator, necessitated by direct electron tunneling through very thin SiO₂, opportunities are being explored to implement Ge transistor technology.

Germanium does not form a stable oxide, limiting its utility in traditional MOS manufacturing methods, but this same property has the advantage of making interfacial oxide layers — a problem when working with Si surfaces — less favorable when placing high-k dielectric films in contact with a germanium surface. Although the integration of high-k gate dielectric materials on Ge may be less problematic than with Si, the ultimate advantage of working with Ge is the carrier mobility enhancement, making it attractive for high-speed circuit applications. Low field electron mobility in Ge is more than double that of Si (3900 vs. 1500cm²/V-sec) and the increase is four-fold for holes (1900 vs. 450cm²/V-sec). PMOSFETs exhibiting high hole mobilities have been recently demonstrated.

Ge is closely lattice-matched to GaAs, thus also permitting monolithic integration of electronic and photonic devices. Ge itself is suitable for near-infrared light detectors in the 1.55µm fiberoptic communication band.

Disadvantages of germanium include its limited availability — and with it, high cost — mechanical fragility, a lower melting point and a lower thermal conductivity relative to silicon. These problems can be alleviated, however, by utilizing layer transfer techniques that are now commonly used in the fabrication of SOI wafers. High-quality monocrystalline Ge films can be exfoliated from seed wafers and bonded to oxidized Si wafers in order to form Ge-on-insulator, or directly to Si. The seed wafers — either bulk Ge or engineered multilayer structures with Ge on top — can be used repeatedly, following surface refinishing, as the source of thin Ge films. Some of the challenges for exfoliation processes include the need to match wafer size, and given the difference in thermal expansion coefficient between Ge and Si, the wafer processing needs to be well engineered. Heteroepitaxial growth of Ge films on Si is also possible, but suppression of defects caused by the lattice mismatch is difficult.

The present device community has limited experience with Ge-based MOSFETs [3, 4], some of which have incorporated the additional benefits of biaxial strain [5]. Some questions about properties of Ge in such applications require further analysis. Ge has a smaller bandgap than Si, which can cause junction leakage problems. The saturated high-field drift velocity of charge carriers in Ge is somewhat lower than that of Si. Further experiments and simulations are needed to fully establish the benefits and trade-offs of modern Ge electronics.

High-resistivity silicon

Material and device developments over the past few years have enabled the production of CMOS and BiCMOS transistors capable of operating at very high RF frequencies. The fabrication sequence of such devices is compatible with standard digital CMOS processing, allowing the monolithic integration of RF circuitry with high-speed logic and memory. This is leading to the emergence of whole new classes of mixed digital/analog devices with wireless communication capabilities.

Most CMOS logic and memory circuits today are fabricated on bulk wafers with resistivity in the range of about 1–20Ω-cm, or epi wafers with a similar epi resistivity on a heavily doped substrate. SOI wafers are also used for both CMOS and BiCMOS devices. The integration of RF circuits into CMOS devices favors a shift to a very high substrate resistivity because unlike digital CMOS, RF circuitry requires linear, analog devices with low noise and precision passive components (e.g., resistors, capacitors and inductors).

Very high substrate resistivity decreases capacitively-coupled crosstalk between digital, analog and RF components, improving noise isolation. It also improves the quality factor of spiral inductors by decreasing eddy current losses, and improves the quality factor of metal-insulator-metal (MIM) capacitors by decreasing parasitic substrate capacitance. "High resistivity" is typically defined as resistivity ≥~1000Ω-cm, although in practice, resistivity >50Ω-cm offers tangible benefits to device performance. The intrinsic resistivity of silicon, ~725,000Ω-cm at room temperature, is the maximum resistivity theoretically attainable.

Production of high-resistivity silicon places three stringent demands on the crystal growth process. First, the intentional dopant addition to the crystal must be very tightly controlled, and the crystal growing process must produce extremely good axial and radial resistivity uniformity. Second, the sources of unintentional doping must be minimized by the careful application of high-purity materials. Finally, the formation of interstitial oxygen (O_i)-related thermal donors during heat treatment in the temperature range of 400–550°C must be suppressed. Since this temperature range is common in backend fab processes, the control of thermal donors formation is vital to obtaining stable, predictable resistivity behavior during device processing.

Float zone (FZ) silicon has traditionally been used to produce very high-resistivity silicon. The FZ process is crucible-less, so that unintentional doping problems are greatly reduced. Because it is crucible-less, FZ silicon is also essentially free of oxygen, eliminating thermal donors. The FZ process also acts as a zone refining process, sweeping out impurities ahead of the melt interface. FZ silicon can be produced with resistivity >10,000Ω-cm. FZ silicon has several drawbacks, however. The emergence of 200mm FZ in the market has been impeded by manufacturing difficulties, and the challenges of producing 300mm FZ are considered by many to be insurmountable. The low level of oxygen in FZ silicon also precludes the use of internal gettering (IG), which is critical to most advanced CMOS device processing, and also decreases the mechanical strength of the wafers.

Czochralski (CZ) growth is preferable to FZ for large-scale production of large-diameter wafers; however, the use of a silica crucible in CZ growth leads to two problems. First, boron is a low-level contaminant in SiO₂ that is very difficult to remove. Consequently, unintentional boron contamination of CZ silicon from even the highest-purity crucibles makes it very difficult to produce resistivities greater than ~5000Ω-cm. Secondly, the crucible introduces interstitial oxygen into the CZ silicon, leading to potential thermal donor formation problems. CZ growth methods exist that can reduce O_i to a level where thermal donor generation is insignificant, but as in the FZ case, these low-O_i wafers do not develop the oxygen precipitation necessary to produce internal gettering nor strengthen the wafer.

Currently, the most promising approach to suppression of thermal donor formation at the higher O_i levels found in standard CZ silicon is to deliberately grow oxygen precipitates in the wafer to consume interstitial oxygen [6] while still maintaining control of the requisite wafer warpage. Growth of a high density of large precipitates can consume enough of the interstitial oxygen to minimize subsequent thermal donor formation. As an added benefit, the oxygen precipitates provide internal gettering in the wafer.

The oxygen precipitation heat treatment can be lengthy, however, adding to the wafer manufacturing cost. Very high-temperature heat treatments (T>1100–1200°C) in the fab can also redissolve some of the precipitated oxygen, increasing O_i and leading to thermal donor formation again, during subsequent thermal processing. Efforts continue to develop a robust and cost-effective manufacturing process that can control thermal donor formation while providing acceptable IG in high-resistivity CZ silicon.

Isotopically pure silicon

Heat removal is becoming increasingly critical in enabling continued improvements in speed and transistor density in high-performance logic devices. One proposal to ameliorate this problem is the use of isotopically pure silicon.

The natural abundance of silicon isotopes is 92.17% ²⁸Si, 4.71% ²⁹Si and 3.12% ³⁰Si. The presence of several percent of the more massive ²⁹Si and ³⁰Si isotopes in a predominantly ²⁸Si crystal acts to scatter the phonons (i.e., lattice vibrations) that transport most of the heat through the crystal, decreasing its thermal conductivity. If the crystal contains isotopes of one mass only, e.g. ²⁸Si, this component of phonon scattering is eliminated, increasing the thermal conductivity, in principle. This isotopic purification of silicon can be achieved by technology originally developed for uranium enrichment, namely gas centrifuge separation of gaseous SiF₄.

In principle, the entire crystal (and hence the entire bulk of the resulting wafers) can be produced of isotopically pure ²⁸Si. The improved thermal conductivity of the die would increase heat transport through the thickness of the die to the package/heat sink, lowering the average operating temperature of the whole die. This approach is prohibitively expensive, however, due to the high cost of isotope separation and the large amount of isotopically pure silicon required to grow a large-diameter crystal.

Alternatively, a thin layer of isotopically pure silicon can be created as the layer of an epi wafer or SOI wafer. In this case, heat transport through the thickness of the die is not improved, so the average operating temperature is not lowered. However, lateral heat transfer within the isotopically pure layer is improved and may help to reduce peak temperatures in localized "hot spots" within the circuit.

The magnitude of the improvement in thermal conductivity of isotopically pure silicon is not clear at present. Early measurements indicated an increase of 60% at room temperature [7, 8]. More recent measurements report only a 7% improvement [9]. More work is needed in order to understand the potential costs vs. benefits of using isotopically pure silicon.

Integrated optoelectronics on silicon

Despite silicon's prowess in most mainstream semiconductor applications, a need is developing to introduce technologies compatible with silicon that enable high-speed optical communications for application within chip, chip-to-chip, and beyond. Techniques akin to packaging (e.g., hybrid chip mounting) address some of this need, but monolithic integration of light-emission, light-detection, and light-routing capabilities with silicon CMOS computing provides the greatest potential for silicon microsystem enhancement. In general, light emission and light detection present the greatest challenges when considering optoelectronic integration with silicon CMOS because of silicon's limited utility in such applications due to its indirect band gap. Although there are many variants in the literature, there are two broad approaches for the integration of light-emission and light-detection communications capability with silicon: 1) alter the silicon microstructure in a way to induce a corresponding change in its energy band diagram, to enable efficient light coupling and conversion, 2) work with interlayer approaches to introduce high-quality photonic materials (e.g., III-V compounds or high-Ge content photodetector layers) on the silicon substrate.

Conclusion

As the Emerging Materials Team continues to evaluate and explore the five areas discussed, the list will be updated on a continual basis. As the technologies condense to the point of requiring targets, they will be incorporated into the roadmap tables as appropriate. For the 2003 ITRS, no roadmap targets for Emerging Materials will be outlined.

Acknowledgments

An additional author of this paper is Neil Weaver, SEH. The authors gratefully acknowledge other members of the Emerging Materials Team, including Rick Wise, Texas Instruments; Jim Moreland, Wacker; Greg Wilson, MEMC; and Doug Meyer, ATMI.

References

1. J.W. Matthews, S. Mader, and T.B. Light, J. Appl. Phys., 41, 3800, 1970.
2. T.A. Langdo, et al., Appl. Phys. Lett., 82, 23, 4256, 2003.
3. Chui, et al., IEDM Tech. Dig., p. 437, 2002.
4. Shang, et al., IEDM Tech. Dig., p. 441, 2002.
5. Lee, et al., Appl. Phys. Lett., 79, p. 3344, 2001.
6. T. Abe and W. Qu, ECS PV 2000-17, pp. 491–500, 2000.
7. W.S. Capinski, et al., Appl. Phys. Lett., 71, 2109, 1997.
8. T. Ruf, et al., Solid State Commun. 115, 243, 2000.
9. A.V. Gusev, et al., Inorganic Materials, 38, 1100, 2002.

Mayank Bulsara is chairman of the Emerging Materials Team and co-founder and CTO of AmberWave Systems; e-mail: [email protected].