Technology News
12/01/2005
Sematech finds first low-k material to pass screening for 45nm
Sematech has reported it has found found a low-k material that passes all its screening tests for 45nm. The two-level metal test structure built with Rohm and Haas Electronic Materials’ spun-on Zirkon has a k-effective value of 2.5, meeting the ITRS 45nm target for 2009-2010, and passes early reliability tests. Processing the stack through CMP before removing the porogens maintains a stronger structure, so the time-to-failure of the passivated 300nm-pitch, two-level metal structure was essentially the same as that of the porous MSQ (k = 2.3) low-k baseline material alone.
“Very few materials make it through to the end of screening, only one or two for each process generation,” says Sitaram Arkalgud, Sematech’s director of interconnect. “This is it so far for 2.5 k-effective without damage.”
The process uses a spun-on MSQ-based dielectric matrix with an acrylic polymer-based porogen thermally stable up to 275°C - the seventh-generation version of the Rohm and Haas material - with a bulk k value ~2.1, along with a spun-on hard mask layer and a CVD dielectric copper diffusion barrier. The stack is processed as a dense material through CMP and reportedly shows no delamination or cracking. Then a UV-assisted thermal cure at 400>°C removes the porogens and further sets the matrix. Though the structure was built using all standard processes, results did depend on switching to a CF4-based etch chemistry and a Cu selective slurry.
Tests showed no detectable penetration of ALD precursors into the two-metal test structure and up to 97% via chain yields (1.08 million 0.13µm vias) after CMP, though yield declined with additional annealing. The difference between the predicted and extracted values of k-effective, a proxy for the amount of sidewall damage, was only 0.2. Time-to-failure matched that of a porous MSQ (k = 2.3) baseline. The hardmask material, however, could have some reliability issues.
Another potential issue is that any dense films in the stack could prevent the porogen from getting out and the UV curing light from getting all the way in. Lead author Ward Engbrecht, Sematech copper low-k integration project engineer, reported the results at the recent Advanced Metallization Conference in Colorado Springs.
Researchers say they’ll now pass along the effort to member companies for commercial development and move on to research on keff levels of 2.1 for nodes even further in the future, though the path is by no means clear. The current solid-first process could potentially be extendable with a lower bulk k value of 2.0-2.1, says Klaus Pfeifer, integration program manager, “but the dielectric barriers would kill us.”
“K-effective is being driven by the assist layers,” Arkalgud notes. “And there haven’t been any great developments there.” Reducing the k value of the dielectric barriers, or decreasing their thickness, means they no longer work well enough to prevent copper diffusion and moisture damage. He figures current integration systems can probably be extended to 45nm, pushing bulk-k values of 2.3 to stacks with k-effective values below 2.5. “But for 32nm, we will need changes in the way we integrate these things,” he argues, “like airgaps or sacrificial dielectrics or lower-k support layers.” - P.D.
EUV lithography takes shape at ASML
Will 13.5nm extreme-ultraviolet (EUV) lithography be ready for production by 2009 as the semiconductor industry moves to 32nm half-pitch device features? With many technical hurdles still to be surmounted, there are plenty of skeptics, particularly since major lithography transitions tend to be as sluggish as wafer-size shifts.
But now, two EUV alpha prototype exposure tools are taking shape at ASML in preparation for shipment to IMEC in Leuven, Belgium, and to Albany NanoTech in the US in 2Q06. The first tool, a 30-ton behemoth (see photo) even without the optical (soft x-ray) source module, has a 1.5m multiply folded optical path between the reticle stage at the top and the wafer stage at the bottom, compared to a 1m path in the most recent ASML 193nm dual-stage stepper/scanner (1400i). Most control software is the same.
 One of ASML’s extreme-ultraviolet (EUV) alpha prototype exposure tools. |
Since essentially everything will absorb EUV radiation, all modules must be operated in vacuum, so an array of vacuum pumps is attached to the tool. This also means that reflective rather than refractive optics are needed throughout the system.
Two conditions must be met for EUV to move into production at the 32nm node. First, an array of huge technical challenges must be overcome so that production-worthy tools with throughput of >100wph can be built. Second, chipmakers must see that EUV tools, probably priced at more than $40 million each, are more cost-effective than high-NA, double-patterning 193nm immersion tools.
ASML executives are confident that both conditions will be met by 2009, but Noreen Harned, VP, marketing, technology, and new business, points out that a full EUV infrastructure will also be essential for commercialization and that major technical challenges, including boosting source power, adapting to the lack of a pellicle, and fabricating the optics, would have to be overcome.
A discharge source rather than an excimer laser source will be used in the prototypes, Harned explains, because it is less complex and more compact, but ASML is keeping options open. A laser source might be scalable to high power but may be more costly. Also, tin has replaced argon as the discharge medium because of much higher conversion efficiency. Power of 27W, needed for the prototypes to reach 10wph at 5mJ/cm2, has been achieved, but output will have to be boosted to four times this level for production tools, according to Harned. Tin should be capable of that. Focusing elements within the chamber have been considered to boost energy at the wafer, but they would add too much complexity, she explains. All discharge debris must be removed to prevent imaging faults. Discharge sources are under development by Philips and a group including Xtreme, Gigaphoton, and Ushio. This group and Cymer are also developing laser sources.
A reticle-handling frame has been developed to move a rigid mask into position; the reticle can be covered at all times except during exposure. A pellicle can’t be used because it would absorb the illumination. Experiments showed the robotic reticle exchange is particle-free.
Multilayer reflective rigid masks have been produced with flatness below 70nm on both sides, but 50nm will be needed for production, says Harned.
Optics are coated with 64 layers of silicon and molybdenum, and they must be polished using picometer (pm) interferometry, with reproducibility better than 50pm rms. Reflectivity has reached 67%, and the goal is 70% or better, according to Harned.
The wafer stage has been integrated, and the dynamic performance of the vacuum prototype is said to be better than current production tools, meeting 32nm node requirements. Pumping to vacuum can take 5-10 hr because of the need to extract moisture from internal surfaces.
There will be no role for 157nm lithography as an interim step, according to Martin van den Brink, executive VP of ASML. A prototype 157nm tool at IMEC has been dismantled, and parts are being used in other stepper/scanners. A 157nm immersion tool would be limited to a maximum NA of 1.3, which would be roughly equivalent to immersion 193nm using a high-index fluid to reach a NA of 1.65, which is a future target, according to van den Brink.
What about using hyper-NA immersion 193nm instead of EUV at 32nm? To do 32nm half-pitch features, according to Kurt Ronse, director of the lithography department at IMEC, would require a NA of 1.9, far above the 1.6 that has been achieved in the lab. A double-exposure approach could also shrink features, but that would cut throughput in half.
The conclusion: 13.5nm EUV will be needed for 32nm, and ASML says it will be ready when 2009 rolls around. - B.H.
Managing process-design interactions in the nano era
Managing process-design interactions becomes an ever-greater problem in the nanometer era of IC fabrication, resulting in design problems and yield losses. An example of this general trend was shown by Cypress Semiconductor researchers at the recent International Symposium on Semiconductor Manufacturing (ISSM) (www.issm.com). “CMOS Vt-control improvement through implant lateral scatter elimination” by Igor Polishchuk et al. showed that threshold voltages of transistors can vary significantly depending on their proximity to a well boundary and that this effect is due to the scattering of implant ions off the sidewalls of photoresist.
Shifts in Vt peak distributions of ~60mV were seen in narrow transistors, triggering an investigation into the root causes. The schematic cross-section of a 90nm-node well during implantation (see figure, part a) shows implant ions (depicted as arrows) on the left side of the structure penetrating deep into the silicon substrate to form a doped well, while the implant ions on the right side are stopped by the photoresist mask. The ions that enter the photoresist near the mask edge undergo random collisions and have a certain probability of escaping from the sidewall of the photoresist. These ions then dope the channel region of a nearby transistor.
A corresponding dopant profile obtained by Monte Carlo simulation (TSUPREM4) is shown in part b of the figure. The dopant concentration at the surface of the silicon near the mask edge is higher (darker shade in the figure) than farther away from the mask edge.
Given that the mask sidewall induces the doping variation, based on both modeling and empirical data, there are three ways to minimize the problem: reducing the sidewall height (i.e., mask thickness), increasing the mask material’s density, or reducing the sidewall angle. Cypress uses a combination of all three techniques, with a hardmask instead of photoresist to both reduce height and increase mask density.
The hardmask can be sacrificial and removed after well implantation, or kept as part of the ultimate transistor structure. A good example of a sacrificial hardmask is the bottom antireflective coating (BARC) layer, which is already often used as a part of the lithographic process. An example of an ultimately structural hardmask is a polysilicon film that later can be patterned to form the transistor gate.
The probability of lateral scattering strongly depends on the slope of the mask, so this parameter should also be controlled. For a vertical sidewall, a single collision is often sufficient to direct ions out of the mask layer. However, since a single collision can only change the direction of an ion by a small degree, if the sidewall angle changes by even a few degrees, it can capture many single-collision ions. Thus, multiple scattering events in the same direction are required in order to “eject” a traveling ion out of the mask layer with even a slight sidewall slope. Corresponding to this multiple event process, the “ejection” probability decreases exponentially with the mask slope angle, dropping nearly an order-of-magnitude for a decrease in slope from 90° to 80°.
The clever use of a structured hardmask in the process module significantly tightens the distribution of transistor performance. The process had previously created FETs with a Vt distribution of 305-380mV, while the same mask-set using the new process created FETs with a narrowed Vt distribution of 305-340mV.
Without tighter Vt distribution, circuit design would require sophisticated device models to predict Vt based on a specific layout. In addition to intrinsic calibration issues with any model, having to iterate between logic schematics and physical layout adds unacceptable time to the design cycle. The only way to make the circuit design truly immune to this problem is through process solutions. - E.K.
Biotechnology enables high-quality polysilicon film on glass
Researchers at the Nara Institute of Science and Technology (NAIST) in Japan say they’ve made high-quality polysilicon film on glass with carrier mobility matching that of single-crystal silicon by wrapping the seed crystals in protein.
A ferritin protein casing enables the creation of an evenly spaced array of large seed crystals, from which polycrystalline silicon, with carrier mobility of several hundred cm2/Vs, can be grown. The high carrier mobility could potentially enable the production of high-speed thin-film transistor displays, or even allow the supporting logic and memory circuits to be made directly on the glass panel.
 Casing of ferritin protein enables creation of large Ni2Si seed crystals for growing high-quality polysilicon film on glass. (Source: NAIST) |
A glass substrate is topped with a 50nm layer of amorphous silicon, then coated with a solution containing 7nm cores of Ni ions encased in ferritin. Heating the material to 110°C drives off the ferritin, and the Ni reacts with the Si to form Ni2Si seed crystals. Then the glass is annealed at 550°C to crystallize the silicon.
Carrier mobility is significantly improved because the diameter of the seed crystals is ~3µm, an order-of-magnitude larger than those previously used for crystallization at this temperature. The protein also reacts with the Si during curing, pushing the Ni cores into a fairly regular 2-3µm spacing. The Ni apparently moves to the seed crystal boundaries where it has little influence on the quality of the polysilicon film.
- SST partner Nikkei Microdevices
Mitsui High-tec replaces package substrate with etched copper
Mitsui High-tec proposes replacing expensive organic package substrate with a sheet of etched copper-lead frame alloy, to make a package with close to the high pin count of a ball grid array package, at close to the low price of a quad flat package.
Key to the approach is a clever scheme for partially etching out copper studs before encapsulation, then completing the process after the studs are fixed in resin. Mitsui uses standard copper-lead frame alloy and processing tools, coating the copper substrate with photoresist and exposing and developing a pattern of pads or posts on both sides of the sheet. The tops of these studs are plated with gold, and the copper in the spaces between them is then etched out from the top, down to halfway through the sheet. The chip is then bonded with gold wire to these posts, and the whole unit is encapsulated in resin. Finally, the rest of the copper substrate between the studs is etched away from the back, down to the resin, leaving an array of copper studs protruding from the bottom of the package like a ball grid array.
 Mitsui High-tec replaces the package substrate with etched copper. (Source: Mitsui High-tec) |
“No new capital investment is required,” says company VP Katsufusa Fujita. “Package cost is about 30% less than a BGA.” The company sees applications for products such as cell phones and portable music players for the packages that range from 4-12mm2, with pin counts from 40-304 pins. The company started pilot production and reliability testing in late 2005, and plans to start commercial production next fall.
- SST partner Nikkei Microdevices