Semiconductor suppliers turn to DFM at nanometer nodes
12/01/2005
By Mark Miller, Pankaj Mayor and Walter Ng
Design decisions made early in IC development can either complicate or alleviate a growing number of manufacturing challenges in advanced process technologies as feature sizes shrink well below 130nm. Moreover, the proliferation of third-party ASIC designs and fabless semiconductor strategies has raised additional challenges by separating product development from manufacturing at independent foundries.
Thus, leading semiconductor companies are integrating more manufacturing-aware capabilities into design flows to manage an array of issues arising from sub-100nm process technologies and subwavelength lithography. This is leading to closer collaboration with electronic-design automation (EDA) suppliers to create EDA software tools that can “dial in” details about advanced manufacturing technologies and new materials. The aim is to ensure that designed structures comply with downstream manufacturing concerns for line spacing, orientation, and other factors.
For years, design engineers could apply conventional sign-off methods to confidently move new products into production, relying on manufacturing operations to optimize yields after IC layouts were done. With processing nodes heading to 90nm and below, semiconductor manufacturers face new electrical and physical effects that dramatically complicate design and erode the ability to achieve early working silicon. Optimizing performance in new designs also has become more complex due to the growing deep-submicron effects (Fig. 1).
Below the 130nm node, increased leakage currents boost power consumption, driving a trend toward lower supply voltages. The combination of closely spaced interconnect lines and higher operating frequencies in ICs increases the potential for signal integrity (SI) problems, such as crosstalk and coupling in devices that already require lower noise margins due to reduced supply voltages. At the same time, designers need to account for downstream manufacturing effects, such as the potential for metal-line distortion from chemical mechanical planarization (CMP) processes and stronger resolution enhancement techniques (RET) in photomasks for subwavelength lithography. Designers must anticipate the impact of these manufacturing technologies on critical timing paths in ICs.
Attempts to address the combination of these effects solely by correcting post-layout manufacturing data are proving ineffective. As a result, problems encountered in the manufacturing stage typically require additional design iterations and “silicon respins,” which not only means million-dollar mask costs but also a delay in product revenues in competitive, fast-moving markets. Consequently, leading semiconductor suppliers are turning to more effective design-for-manufacturing (DFM) strategies that will help them anticipate and address wafer-processing concerns.
Dealing with accuracy
In the past, most manufacturing requirements were addressed by running design-rule checking tools following tape-out of new chip designs. Now, designers need new tools and methods to more accurately analyze the effects of power issues, SI, and manufacturing on circuit performance during device development. In turn, effective analysis depends on the availability of accurate, comprehensive characterization of advanced processes in the form of design-rule sets and technology files.
In earlier, more forgiving process generations, chip designers could compensate for modeling approximations and estimated layout parasitic data by building in sufficient timing and layout margins to ensure success in functional silicon and nominal yield. In advanced technology nodes, however, nanometer effects and manufacturing variations can erode performance beyond any reasonable margins designed into circuits with conventional tools and methods (Fig. 2). Estimated parasitic data and modeling approximations used in traditional methods lack the accuracy needed to uncover timing variations arising from these nanometer effects and manufacturing variations.
Traditional parasitic extraction tools create simple patterns for parasitic resistance-capacitance inductance data by systematically analyzing a number of interconnect patterns. In this approach, a field solver builds a table of results with specific parameters of wire width and spacing. In turn, parasitic extraction tools need to interpolate any width and spacing values that fall between the calculated values. During detailed timing analysis of design performance, these inaccurate parasitic values can allow timing problems to pass undetected in the design stage, resulting in poor performance or even circuit failure in actual silicon.
Wire modeling
Moving forward, extraction methods must account for an increasingly array of interacting factors, including new models of wire performance found in advanced processes. For example, traditional aluminum interconnect lines are shaped differently than copper-processed wires, which use a cladding layer to shield copper metal from the surrounding dielectric insulator. In cladded wires, current flows more easily through the copper portion of the interconnect lines, while the outer surface of the cladding largely determines capacitance. Thus, effective wire dimensions for resistance differ from those for capacitance.
Wire modeling also becomes more complex due to manufacturing effects such as CMP, which can introduce wide variation in the resistivity of individual wires. In dual-damascene copper processes, CMP polishing can wear down the tops of wires. Differences in copper thickness introduce variable interconnect resistance and capacitance across the die, leading to variable parasitic delay, even for wires of equal length. Furthermore, capacitance can easily double with processing-enhancement methods that use “dummy” metal fill to increase uniformity in CMP polishing across a chip and entire wafer. As a result, the actual resistance and capacitance of a functioning interconnect wire depends on its local environment, including any dummy structure located several microns away.
Today’s advanced extraction tools use field solvers to analyze accurate models of interconnect patterns and determine a wire’s actual parasitic capacitance. Using detailed data from foundries and wafer fabs, these tools provide 2D and 3D modeling and characterization of advanced dielectrics, trapezoidal conductors, copper technology, potential CMP distortions, and other performance-altering effects. Advanced extractors are able to account for these on-chip variations, providing accurate parasitic data needed for reliable timing analysis and simulation in design. Emerging methods, such as process-rule encryption, allow third-party foundries to securely provide customers and EDA vendors with the necessary data for accurate wire modeling and parasitic extraction.
Growing design influence
Increased collaboration between manufacturing operations and EDA vendors is beginning to influence all areas of DFM-capable design flows. For example, emerging capabilities help design engineers play a greater role in optimizing circuits and chip features for more sophisticated RET structures on photomasks, which are needed in subwavelength lithography for 90nm and below technology nodes. In the past, manufacturers could apply RET technology to alter GDSII mask manufacturing data without requiring any participation by design engineers. In this approach, methods such as optical proximity correction and phase-shift mask technologies help maintain the fidelity of smaller geometries for a given wavelength of light, but this is becoming more difficult to do as feature sizes shrink and processes continue to use 193nm ArF scanners.
With the migration to subwavelength lithography, imaging through a diffraction limited system results in severe distortions of patterns printed on silicon compared to those created in the physical design steps. Distortion effects impact pattern fidelity and edge placement on silicon. In the worst case, they can eliminate patterns entirely (Fig. 3). Other process steps, such as etching and oxide growth, exacerbate the distortion between drawn and printed shapes. Unless those distortions are corrected, inaccurate device-image printing will result in significant yield losses.
Conclusion
Emerging EDA tools can help designers avoid potential production problems early in development, before completed designs are taped out for mask sets. With increasingly complex process technologies, ensuring design manufacturability requires greater involvement and interaction among all members of the semiconductor supply chain, including chip designers, intellectual property vendors, EDA vendors, and fabs.
Contact Mark Miller at Cadence Design Systems Inc.; ph 408/894-2961, fax 408/944-0747, e-mail [email protected].
Pankaj Mayor, Cadence Design Systems Inc., San Jose, California
Walter Ng, Chartered Semiconductor Manufacturing Ltd., Singapore