Using DFM hot-spot analysis for predicting resist patterns
12/01/2005
As process tolerances decrease, significant yield losses are observed specifically due to differences between the design layout and how the resist actually prints on the wafer. To reduce cycle time and costs, engineers responsible for resolution enhancement technology (RET) and optical proximity correction (OPC) need to correct these differences with highly accurate analysis prior to manufacturing the reticles. This work presents a design-for-manufacturing (DFM) approach that predicts the resist pattern by applying a rigorous simulation model and enables the simulation of cells larger than 15×15µm with full accuracy at the resist level.
By Peter Brooker, Hans Koop and Hartmut Marquardt
The minimum feature size of ICs continues to shrink with each generation of semiconductor process improvements. As transistors and metal lines get smaller and move closer together, previously insignificant third-order variables now dominate IC design and fabrication. Designers find deep-submicron chips much harder to design and get working at first silicon, and they also need more mask re-spins to get adequate yield during manufacturing. In fact, manufacturers have found that by 90nm, only ~50% of designs operated as expected and required one or more mask re-spins to achieve acceptable yield and performance [1].
Design issues
Some of the underlying challenges driving yield and re-spins are design-related constraints such as device size, speed, power, electromigration, leakage, noise, and signal integrity. These issues typically are addressed by constraints and guidelines established early in the design phase.
As process tolerances shrink, statistical variations in simple parameters become more important. Variations in parameters such as gate oxide thickness, dopant variations, and line-edge roughness become too large to guardband. Layout pitch and orientation, and edge and corner proximity also strongly affect device electrical performance. Design rules or recommendations, alone, are no longer enough to ensure acceptable yield.
Design-for-manufacturing
In earlier days, designers worried about speed, power, and area. They could leave the yield issues up to manufacturing to solve. However, with deep-submicron processes, chip designers now must trade off speed, power, area, and yield.
Currently, designers have few tools beyond re-spin trial and error to help predict how their design changes will affect yield. As a result, DFM issues dominate the design constraints and tradeoffs. One significant DFM challenge arises in the microlithography areas that print the IC patterns on the wafer, where continual improvement of lithographic capability enables the production of smaller critical dimensions (CD) for the semiconductor devices. Unfortunately, the methods for producing the smaller CDs are not robust against process variation, and the yields are initially low.
Lithography gap
One reason for the low initial yields for smaller CDs is that the wavelength of the exposure tools has not kept up with the progress of the semiconductor processing capability. The pattern geometries produced on the wafer are often smaller than the wavelength of the exposure tool. This disparity creates challenges in producing an accurate image of the reticle on the wafer.
Development continues with shorter-wavelength light sources including deep ultraviolet (DUV) at 248nm, 193nm, and extreme ultraviolet (EUV) at 13.4nm. Even so, a “lithography gap” continues to exist between the IC dimensions needed and the wavelength of available light sources.
Resolution issues
RETs make design shrinks possible without the need to reduce the wavelength of the exposure tool. Such technologies include phase-shift masks (PSM) to reduce or avoid interference patterns, and OPC to compensate for problems such as line shortening and corner rounding. In OPC, chrome edges on the mask are iteratively moved until the resist edges match the desired layout as closely as possible.
Process variations adversely affect yield for designs with high levels of RET. Typical lithography process variations include the parameters of optical focus, dose (light intensity), and the composition and thickness of chrome, resist, and antireflective coatings. Other variables include the mask and wafer surface topography and flatness. These all affect the real 3D shape of the resist, such as trench depth, sidewall slope, and resist CD width at the trench bottom, and must be considered for DFM.
Microlithography issues
Design software automatically generates the target layout for the transistors on the chip. These target layouts are usually in the form of GDSII files. The RET/OPC engineer then uses RET/OPC software to modify the layout so that the actual printed resist matches the target layout as closely as possible. Microlithography DFM issues occur during this transition from the design target layout to the mask layout generated by RET/OPC. The combination of resist process variations and RET/OPC effects results in problems in the final resist patterns that include pinching or bridging, via-to-contact misalignment, and line-end shortening. Therefore, the actual resist patterns differ from the desired patterns as described by the target layout. DFM requires that designers and RET/OPC engineers analyze these “hot spots” and alter the design or mask patterns to eliminate them.
Lithography simulation/image verification
As noted previously, unless engineers correct DFM problems before maskmaking, there is a high cost in dollars and time-to-market. To reduce cycle time and costs, designers need highly accurate DFM solutions to find, quantify, and fix these problems before committing to manufacturing masks and silicon. Therefore, there is great interest in verification to ensure that the final resist patterns on the wafer both match the required design geometry and are manufacturable.
Different techniques are being used for full-chip simulation and detailed hot-spot analysis. All full-chip simulation approaches have to trade off simulation speed and area size at the expense of accuracy. Solving yield problems caused by microlithography requires high accuracy.
Traditional hot-spot analysis
Full-chip image verification products simulate the aerial image at the wafer over the entire design. They use the aerial image along with simple resist models to make predictions of where the resist edge occurs. Usually, hot spots are detected by comparing the location of the simulated resist contours with the desired target layout.
Currently, the tools that determine the hot spots also are used to try to fix them. Consequently, the RET/OPC engineer has only a coarse prediction of the resist edge location, with no information on its shape. Due to the approximations used to predict the resist pattern, fixing detected hot spots has consisted of trial and error.
Analysis of hot spots requires getting an accurate view of how the final resist geometry differs from the intended design geometry. Although a traditional lithography simulator such as Solid E can generate an accurate 3D resist profile, such simulators are typically limited to areas <1×1µm. Truly effective DFM hot-spot analysis requires full-accuracy lithography simulation of areas >10×10µm. Accurate full 3D resist models calibrated over a range of resist process variations also are critical to the success of the hot-spot analysis.
Advances in hot-spot analysis
Recent improvements in numerical algorithms have enabled a significant increase in the area on the reticle that can be simulated at full accuracy. RET/OPC engineers can now generate accurate, full 3D resist profiles on areas >15×15µm in <30 min using tools such as Solid+.
RET/OPC engineers or designers do not have to calibrate the resist models because validated models are automatically available via a shared database used by photoengineers during traditional lithography simulation for process development. Figure 1 shows how the hot-spot simulation analysis approach fits into existing design flows. It also provides the communication bridge between the design and mask/OPC development.
 Figure 1. Lithography process flow. |
In addition to a nominal parameter set, engineers can model the lithographic process over a range of parameter variation. This approach allows the analysis and display of the impact of varying the geometry or the effect of process variations on the resist profiles of the hot spot, thus providing manufacturability analysis of multiple hot spots.
 Figure 2. CD contour nonoverlap. Contours of CD +10% and CD -10% for a metal line at two locations are shown. |
Figure 2 shows an example of a hot spot in which a metal line needs to have the same CD at two critical locations. To construct the figure, simulation is used to predict the resist CD at the two different locations. In the plot, contours are displayed of the optimal CD +10% and the optimal CD -10% for both locations. There is no overlap at the center of the CD process windows, so engineers can now modify the layout until the process windows overlap. Choosing a solution that maximizes the process window overlap will ensure that the device can be manufactured with adequate yield.
Large-area hot-spot simulation
Advances in the algorithms associated with the Abbe formulation of the aerial image have made possible great reductions in the calculation times for large areas. Figure 3 shows a comparison of the standard Abbe to the new Abbe algorithm for area sizes starting at 1×1µm.
 Figure 3. Calculation times vs. area for new and standard Abbe algorithms for small areas. |
From Fig. 3, it is seen that as the simulation area increases, the ratio in calculation time between the old Abbe algorithm and the new one grows exponentially. Although not shown on the graph, execution time for generating a 15×15µm area at high pupil mesh resolution takes 20 min for the new Abbe and >180 hr for the standard Abbe algorithm. This represents a decrease in calculation time of >500×. The plot in Fig. 3 was done at the coarsest resolution permitted for the illumination source. If a finer resolution is used, the calculation will be more accurate, but will take significantly longer to complete.
Figure 4 illustrates the tradeoff of computation vs. accuracy. Given a 3% error tolerance, the new Abbe is 10× faster than the standard Abbe. For applications that require a 0.3% error, the new Abbe is 1000× faster than the old.
Conclusion
Desing-for-manufacturing requires that designers and RET/OPC engineers correct the lithography problems associated with detected hot spots before committing to manufacturing masks. Software is available that can model the full 3D resist profiles for areas >15×15µm and enable DFM analysis of all detected hot spots. It is also possible to analyze the effect on resist profiles of changes in layout geometry as well as quantify the robustness of the resist profiles due to any observed lithography process variation. The full 3D resist models are automatically calibrated from a resist process development database and shared with traditional photolithography process engineers.
Acknowledgments
Solid E and Solid+ are trademarks of Sigma-C.
Reference
- M. Miller, “Nanometer Yield Enhancement Begins in the Design Phase,” ED Online, Fig. 2, International Business Solutions 2003 graph.
Peter Brooker received his PhD in fusion plasma physics from the U. of Wisconsin-Madison, and is senior application engineer at Sigma-C Software AG, 4699 Old Ironsides Dr., Suite 210, Santa Clara, CA 95054; ph 512/844-3719, e-mail [email protected].
Hans Koop received his PhD in physics from the U. of Bochum, Germany, and is a corporate application engineer at Sigma-C Software AG, München, Germany.
Hartmut Marquardt received his diploma in physics and PhD in semiconductor physics from the U. of Freiburg, Germany, and is product marketing manager, DFM, at Sigma-C Software AG.