Analyzing damage from ultralow-k CMP
11/01/2005
Introduction of porous ultralow-k (ULK) materials poses challenges, such as poor mechanical properties due to porosity, that affect all unit processes, including CMP. Minimizing and eliminating low-k damage are the primary concerns. CMP-induced ULK damage on blanket, single-level, and multilevel metal stacks was studied using surface, spectroscopic, and electrical characterization techniques.
As the industry strives to reduce interconnect RC delay, focus has shifted to the reduction in overall stack capacitance through the integration of new ULK materials into the dielectric film stack. Materials with intrinsic k values in the range of 1.9-2.4 have been achieved by introducing porosity between 20% and 50% of the low-k dielectric. Performing chemical mechanical planarization (CMP) processes on such mechanically fragile, absorbent materials without significant damage to the dielectric stack is becoming a challenge. A thorough assessment of damage contributions for each unit process is invaluable in progressing toward a keff goal of 2.5 as required by the International Technology Roadmap for Semiconductors (ITRS) for the 45nm node [1]. Different damage mechanisms from the feature scale to the wafer scale are examined.
Materials and processes
The low-k material used in this study is Sematech’s baseline porous low-k MSQ-based spin-on dielectric. It has a k value of ~2.2, with ~40% porosity. The modulus is ~10% and the hardness is ~15% that of conventional TEOS oxide. For single- and dual-level stacks, higher-k SiC was used as a hard mask for the etch and polish stop. The CMP tool used was a conventional rotary platform for both 200mm and 300mm. Industry-standard, conventional, abrasive-containing slurries were used for both copper and barrier polish, along with a standard IC pad for Cu polish and Politex for the barrier polish. Low-pressure, low/medium platen-speed processes were used for polishing. Brush cleans with an acidic clean chemistry were used for post-CMP cleaning.
Structural and chemical changes
Structural and chemical modifications from CMP were studied by polishing low-k blanket wafers. The effect of Cu slurry was not studied because the low-k material is expected to be polished only by the barrier slurry. The damage from the entire CMP unit operation can be partitioned into the following: slurry exposure, slurry exposure with mechanical force (CMP), and post-CMP clean exposure. The experimental splits were designed to provide a better understanding of these effects. Wafers were dipped in slurry for 30 sec and 60 sec, to evaluate the effect of exposure to slurry chemistry, and then were cleaned. Polish was performed for 30 sec and 60 sec and the wafers were cleaned again. Finally, unpolished wafers were processed just through the cleaner. Contact angle, material removal, and Fourier transform infrared (FTIR) spectroscopy data were gathered before and after processing.
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Table 1 shows the split lot results for contact angle and material removal. No significant material is removed either from slurry exposure or clean-chemistry exposure - the static etch rate of the porous dielectrics in barrier slurry is negligible. The low-k removal rate during CMP is >2400Å/min - about 4× that of the oxide removal rate (640Å/min) under these processing conditions. Although the slurry used in this case was a typical low-selectivity (to oxide dielectric) slurry, similar results have been obtained for highly selective slurries. Barrier slurries would have an extremely high rate of dielectric erosion if direct CMP were to be performed on the ULK material.
Contact angle changes indicate a decrease in the hydrophobic nature of the dielectric surface with any processing. Cleaning has a small effect, while exposure to slurry has a slightly greater effect. The major change in contact angle occurs during CMP, when the surface becomes almost hydrophilic. It is interesting to note that the effect of CMP time is not as significant; any surface modification takes place in the first few seconds of CMP. Also, the contact angle is >30° compared to typical values of <20° for oxide, indicating the surface is not completely modified into a silica-like surface.
 Figure 1. Effect of process and process time on FTIR peak ratios of SiCH3 to Si-O-Si. |
Damage involves loss of methyl groups and gain of siloxy groups; thus, the ratio of SiCH3 to Si-O-Si is a good indicator of chemical integrity [2]. This aspect was studied using a spectroscopic technique. The FTIR spectra were gathered; the peak heights were normalized for thickness; and the area under the peak was calculated. The change in the ratio of the two peak areas is considered to be a good indicator of low-k damage. Figure 1 presents this ratio as a function of time for slurry dip (exposure) and CMP. It is observed that exposure to clean chemistry and slurry alone does not cause any modification of the material; the peak ratio, however, is drastically reduced by CMP. The loss of SiCH3 continues with increasing polish time, possibly indicating the creation of an increasing thickness of the damage layer.
Electrical property modifications
We studied the changes of electrical properties through both metal-insulator-metal (MIM) capacitors and single-damascene serpentine comb structures. MIM capacitors were built on blanket wafers that had undergone the CMP slurry exposure and post-CMP clean exposure splits discussed previously. The process involved standard dielectric-cap deposition followed by aluminum-dot metallization and etch. Capacitance was measured on these structures and the k value of the low-k dielectric was extracted from location-specific dielectric thickness. Furthermore, breakdown voltage of these capacitors was also studied by ramping the voltage at 3V/sec until failure.
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No significant change in breakdown voltage was observed between the different splits. At low fields, however, there was a difference in the leakage behavior. Table 2 shows the k values and leakage for the various splits. The leakage values at a nominal 2mV/cm are presented.
There is a marginal change in k value with direct processing. The wafers that have undergone full CMP have slightly higher k than the control (~3%), and the trend is toward higher k for longer CMP times. A stronger correlation exists for leakage. The unprocessed wafer had the lowest leakage, while the wafers with just slurry exposure and clean-chemistry exposure had ~2.5× the leakage of an as-spun low-k wafer. The wafer processed by CMP for 30 sec had ~2.8× the leakage of an unprocessed wafer, while the wafer processed for 60 sec had ~4.8× that of an unprocessed wafer. No clear trend exists for slurry exposure and clean times. The exact analysis is complicated by differences in absolute dielectric thickness between the CMP-processed and unprocessed wafers, and the thickness of the damaged layer, both of which could have an effect on leakage.
MIM capacitance involves capacitors in series (“damaged” ULK and “undamaged” ULK), while line-to-line capacitance in interconnects involves capacitors in parallel. The contribution from the damaged layer (if any) is cumulative for parallel capacitors, but tends to be underweighted in series capacitors. While MIM measurements are useful for monitoring bulk changes in capacitance or k value, CMP damage to ULK needs to be measured as changes in interline capacitance.
To study the CMP damage in real situations, single-damascene (M1) short flow structures were built with SiC as the etch stop layer and hard mask. The nominal line and pitch dimensions of the tested features were 125nm and 300nm, which correspond to the 90nm node. The hard mask is needed for a number of reasons including etch/ash selectivity, lithographic reworking, and polish stop. The presence of this higher-k material is necessary but not desirable, and it is preferable to thin this layer or even remove it completely. Along with obtaining the lowest stack capacitance, thinning or removing the layer also helps improve topography [3]. A series of wafers were polished for incrementally longer times to thin and remove the hard mask and each wafer was electrically tested for interline capacitance. The remaining hard mask was then measured by cross-section scanning electron microscope (X-SEM). Figure 2 shows the capacitance and hard mask remaining as a function of barrier polish time.
 Figure 2. Capacitance and residual hard mask thickness as a function of barrier polish time. |
As expected, the hard mask thickness decreases with polish time and is completely removed after 160 sec for the process used. Capacitance decreases with hard mask thickness (a function of both the decrease in stack height and the decrease of the higher-k contribution of the hard mask) and reaches a minimum with the thinnest residual hard mask, but then increases. Theoretical calculations using both simple classical capacitance as well as the more sophisticated Raphael simulations result in decreasing capacitance with decreasing ULK stack height. This difference clearly indicates an increased k value of the dielectric by direct processing on the ULK. Possible reasons for this include moisture absorption, which could be partially reversible, or the creation of an irreversible chemically modified layer. While the exact nature remains unknown, these results suggest that CMP directly on ULK dielectrics needs to be avoided.
Loss of stack integrity
 Figure 3. Example of a wafer with die-scale delamination at the edge. |
Wafer-level delamination is another mode of damage that is particularly applicable to CMP; Figure 3 shows a wafer with die-scale delamination. Due to the pressure and shear applied, the various layers tend to peel off during processing.
The different modes of failure caused by delamination are characterized and illustrated in Fig. 4. The low mechanical strength of these porous films makes them prone to cohesive failure; the locations for this kind of failure are indicated as [A] in the figure. This mode is readily seen in blanket wafers as well as in nontiled field regions.
Even a simple two-level, single/dual-damascene stack has about 6-8 interfaces between the different dielectric materials depending on the integration scheme. Any local regions of weak interfacial adhesion can cause these layers to peel away, affecting multiple die. This mode is illustrated in Fig. 4 as [B]. Finally, certain specific regions in the stack that act as high stress points and are the source for much of the catastrophic failures have been identified and are indicated in Fig. 4 as [C]. These weak spots tend to be at the intersection of a trench with a via or a via with an underlying metal layer. Cracks at these levels tend to propagate for larger distances because the via level cannot be filled by tiling structures. Cracking at the via level is especially difficult to identify because it will not result in any visual failure, but will show up during electrical testing of via chain continuity.
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It is to be expected that a “gentler” CMP process, incorporating lower pressures and lower shear, is the preferred path toward eliminating delamination. It was observed that low pressures -~1.5psi or less - combined with low table speeds - ≤35rpm - usually lead to delamination-free wafers [4]. However, throughput constraints offered by such processes must be addressed. The choice of slurry and pad also plays a role in minimizing delamination because friction generated during the CMP process is determined by the characteristics of the pad-slurry-wafer interaction. Almost no process window for abrasive-free liquids was seen, compared to a narrow but usable window for conventional abrasive slurries.
Conclusion
Effects of CMP processing on integrated ULK stacks have been evaluated and some key contributors to the damage of these stacks have been identified. It was observed that direct CMP on MSQ-based porous low-k leads to degradation of chemical and electrical properties. Methyl groups are replaced by siloxy groups, accompanied by an increase in dielectric constant and leakage. The mechanical damage from CMP is in the form of film-stack delamination, through cohesive and/or interfacial failure. Other possible sources may include stress points within the film. Less aggressive CMP conditions with low-friction consumables are the best ways to address this challenge.
Acknowledgments
The authors would sincerely like to thank Bernd Kastenmeier, Swarnal Borthakur, and Albert Gonzalez for assisting in collection and analysis of data reported here. Thanks also go to Somit Joshi and Gerald Martin for their contributions during their tenure at Sematech.
References
- International Technology Roadmaps for Semiconductors, 2004, http://public.itrs.net.
- N. Klymko, “Vibrational Spectroscopy of Ultralow-k Dielectric Materials,” Future Fab International, Vol. 17, 2004.
- R. Baker, “Topography Control Using Sacrificial Capping Layers,” Solid State Technology, Vol. 47, No.8, p. 33, August 2004.
- S. Hosali, G. Martin, A. Gonzalez, S. Joshi, “Process Development for Copper CMP on ULK Dielectrics,” Electrochemical Society Conf., Oct. 2002.
Sharath Hosali received his PhD from Rensselaer Polytechnic Institute and is a CMP project engineer at Sematech, 2706 Montopolis Dr., Austin TX 78741; e-mail [email protected].
Eric Busch, Sematech assignee, received his BS from Long Island U. and his MS from the U. of New Haven, CT. He is a module manager at Advanced Micro Devices, One AMD Place, Sunnyvale, CA 94088; e-mail [email protected].