Controlling porous low-k damage with decoupled plasma etching

11/01/2005

One of the key challenges in backend integration is damage to the low-k dielectric during etch/ash processes. A decoupled plasma approach offers independent control of the chemical and physical components of these processes and is useful in controlling damage in porous low-k integration.

Damage to the SiCOH layer during low-k integration is largely due to excessive oxidation of the feature sidewall, which depletes the carbon bonds (C-depletion) during the strip and clean step [1-4]. Managing the damage becomes even more difficult for in situ strip/clean due to the etch chamber “memory effect,” in which fluorine-containing chamber wall deposits (left over from the main SiCOH etch steps) desorb during the in situ strip/clean, thereby exacerbating damage to the SiCOH layer [5, 6]. Reduction chemistry has shown some improvement in the electrical performance. However, its low etch rate and inability to ensure the total removal of the etch residue in a high-polymerizing recipe makes it less than ideal [7, 8]. From a manufacturing logistics and chip yield point-of-view, in situ strip and clean with the oxidation chemistry is the preferred choice, if it can be made to work.

Tightness of the chip-speed distribution results from controlling not only the k value, but also the feature’s dimension since both quantities enter the capacitance equation. The shape of the etched feature, such as top corner (shoulder) rounding, depends primarily on the incident ion energy. An etcher using the decoupled plasma approach can offer independent control of the chemical and physical components of the low-k etch/ash processes. While equipment simplicity and reliability are important, the top agenda of the etch supplier ought to be ensuring feasibility - both technical and economic - of the oxygen chemistry in in-situ strip/clean and providing a wide and stable etch process.

Etch process requirements

The in situ strip/clean should be free of wall deposits that contain fluorine. A two-step in situ strip/clean process is therefore envisioned - i.e., the hybrid ash. The first step immediately after the low-k main etch processes is a short, zero bias-power cleaning step to remove the loose polymer deposits from the chamber wall and wafer surfaces. This step eliminates the memory effect of the low-k main etch. The second step is a low-pressure process with radio-frequency (RF) bias power to ash the wafer with controlled isotropic reaction. A decoupled plasma reactor, as depicted in Fig. 1, can meet such a process requirement.

Figure 1. Schematic of a decoupled plasma etcher: The plasma source is a 60MHz capacitively coupled plasma (CCP), and the RF bias controls the ion energy for the excitation of the wafer surface.Click here to enlarge image

The 60MHz capacitively coupled plasma (CCP) source is chosen because it can sustain a high degree of ionization over a pressure range from 5mtorr to the torr range without a high degree of molecular dissociation [9]. The bias frequency, which drives wafer surface excitation, can be 2MHz or 13.56MHz. This decoupled CCP etcher can control the ion energy of wafer surface excitation independently from the generation of the plasma species. At 0W bias power, the wafer surface is floating with the plasma, and the ion energy is essentially the ion thermal energy.

The ability to control independent ion energy is also crucial for the dual-damascene low-k main etch steps and the etch stop layer (ESL) etch step to obtain optimal top-corner rounding and minimize low-k thickness loss in the features, and will become even more important when porous low-k comes into the picture. Regardless of the applications, it must be possible to control the “bad” plasma damage to the sidewall of the porous low-k, while allowing the “good” plasma damage to occur [10]. The undesirable plasma damage is the sidewall C-depletion, and in the worst case, physical loss of the material through lateral etching. The desirable plasma damage is surface pore-sealing densification through the physical collapse of the porous low-k matrix. Therefore, the porous low-k etch/ash processes could be more easily optimized if the ion energy and plasma species were independently controlled.

Effect of in situ strip and clean

The first step (ash-1) of the oxidation chemistry hybrid ash takes place at zero bias power and usually in a medium pressure range (e.g., 20mtorr). Its optical emission endpoint (OES EPD) signal is shown in Fig. 2a. Subsequent cross-section SEM inspection of the wafer confirms the removal of the CFX deposits from atop the photoresist pattern that occur as a result of the low-k etch step. Pressure and flow are the main factors working on process optimization (e.g., the excited molecular oxygen O2* and O concentration) for the complete removal of the CFX coating from the chamber wall and from the wafer feature surfaces, without digging into the low-k sidewall. A CFX-free chamber is critical for the second step (ash-2) to ensure both minimal ESL loss and low-k feature distortion. The second step strips the photoresist pattern with bias power; its corresponding OES EPD signal is shown in Fig. 2b.

Figure 2. Optical emission spectroscopy endpoint detection (OES EPD) for the hybrid ash: a) 0W-bias ash-1 removes CFX, and F levels out at ~18 sec; b) ion-assisted low-pressure ash-2 strips/cleans the wafer; CO levels out at ~15 sec from the ash-2 RF-on onset; and 100% over-etch is given for ash-2.Click here to enlarge image

The second step should take place in the low-pressure regime (e.g., 5mtorr) since there is some amount of ion excitation of the feature sidewall upon grazing-angle interaction. A small and controlled amount of via sidewall excitation at low pressure is important to ensure the total removal of any cross-linked polymer deposits that were not removed in ash-1. The key in ash-2 is to have a controlled anisotropy of surface excitation and a reduced isotropic (thermal) O flux [11].

The ion-flux-to-O-density ratio (Γi/O) is maximized in the low-pressure regime, as verified by optical emission actinometry and multigrid electric probe measurement. The chemical damage to the low-k sidewall is minimized in the regime of maximum Γi/O. Figure 3 shows a dense low-k via array through all its etch process steps in one continuous sequence (low-k etch steps and hybrid ash): organic ARC open, oxide hard-mask open, main etch, over-etch, ash-1, and ash-2. The ESL loss was 2nm after the low-k etch steps, and 12nm with 130nm bottom CD after the entire sequence.

Figure 3. The etch stop layer (ESL) loss is 2nm after the low-k etch steps (BARC-open + oxide-open + main-etch + over-etch). The hybrid ash immediately follows the low-k etching. The final result for the entire sequence is top CD = 175nm, bottom CD = 127nm, and ESL loss = 12nm.Click here to enlarge image

Wafer ashing in a CFX passivated chamber causes faceting and ESL loss due to CFX outgassing. Even more adverse, CFX outgassing makes the low-pressure, ion-dominated strip step hard to control, resulting in side-etching of the low-k and, at a minimum, C-depletion on the feature sidewall. For example, in a separate experiment with the wafer processed in a CFX-loaded chamber (i.e., ash-1 is eliminated), the ESL loss was 36nm with 165nm bottom CD. The above example of oxidation chemistry is a simple O2-based mixture. There are other non-O2 mixture oxidation chemistries that can achieve the same etch rate (ash-2) as that of the O2-based mixture, and with an even wider process window of preserving the low-k sidewall. Regardless of the choice of gases in the oxidation chemistry (or even for reduction chemistry), the ash-2 step must be CFX-free. The etch rate of the oxidation chemistry is several times higher than that of the reduction chemistry and, more important, the low-pressure regime (maximum Γi/O) oxidation chemistry can clean up the cross-linked polymer more effectively than the reduction chemistry does.

Effect of ion energy

For the via-first example, the top of the via is under ion excitation during the trench etch and the via top corner gets the highest etch yield under the ion bombardment; as a result, its top corner could get rounded. Figure 4 shows the ion energy effect on the dual-damascene via in the decoupled etcher. Figure 4a is for a low 60MHz source power and a low 2MHz bias power (self-bias VDC ≈ -500V); Fig. 4b is for a high 60MHz source power and a low 2MHz bias power; Fig. 4c is for a high 60MHz source power and a high 2MHz bias power (self-bias VDC ≈ -900V). The via top corner becomes severely eroded under high ion energy (Fig. 4c), and the situation is exacerbated by high plasma radical density (Fig. 4b).

Figure 4. Effect of ion energy (2MHz bias power) and plasma radical density (60MHz source power) on the via shoulder: a) low 60MHz source power and low 2MHz bias power (VDC ≈ -500V); b) high 60MHz source power and low 2MHz bias power; and c) high 60MHz source power and high 2MHz bias power (VDC ≈ -900V).Click here to enlarge image

An optimal low-k profile is readily achieved in the decoupled etcher due to its ability to control the plasma species separately from the ion excitation (RF-bias) of the wafer. Although the bottom-only CCP’s process could be adjusted for a reasonable low-k trench profile, its resulting ion energy could become inadequate for the via top corner. This is verified with experiments comparing a decoupled CCP against a bottom-only CCP with their respective optimized processes. For example, the decoupled CCP’s optimal plasma condition is obtained at a source power of 1800W (60MHz) and its optimal ion-energy condition is obtained at a bias power of 100W (2MHz).

The ion energy of the 100W (2MHz) bias is adequate, producing a good trench profile without causing much via top-corner rounding and maintaining a good via top CD. On the other hand, the bottom-only CCP’s optimal plasma condition (for trench profile, selectivities, etc.) is obtained at 1500W of RF power (supplied through the wafer electrode). Its resulting ion energy at 1500W is too high, making the via top corner so severely rounded (the via top CD has become too wide) that two adjacent vias are almost joined.

For the ESL example (e.g., SiC ESL open), minimum alteration of the existing low-k via dimension is required. The via top corner should not be severely rounded; the via profile should not be changed; and the ESL-to-low-k selectivity should be high. Therefore, the ideal etcher should be able to supply the adequate plasma species independently from the ion energy. This situation is shown in Fig. 5 with a reasonably optimized 60MHz source power (plasma species generation) and a medium-level 13.56MHz bias power. Here, the via top corner and its profile are preserved and an ESL-to-low-k selectivity of 12 is achieved. This via’s top/bottom CDs have slight positive bias due to the higher pressure of this particular recipe; the CD bias is much reduced in a lower-pressure regime.

Figure 5. Example of ESL (e.g., SiC) etching. This recipe’s pressure and 60MHz source power were not optimized, and the bias power was set at “medium” level. The result is top/bottom CD bias = +7nm/+13nm, shoulder loss = 18nm, SiC/low-k selectivity = 12.Click here to enlarge image

In another experiment with a higher 13.56MHz bias power (150W), the via top corner becomes severely rounded and the ESL-to-low-k selectivity drops to 8.9. In a third experiment with an even lower 13.56MHz bias power (50W), the via top corner and its profile are well-maintained and the ESL-to-low-k selectivity increases to 21. Therefore, it is not difficult to anticipate the result for a bottom-only etcher: By the time the correct plasma species concentration is achieved by the bottom power, its resulting ion energy will become too high to meet the selectivity and low-k dimension requirements.

Conclusion

Using a decoupled plasma approach offers independent control of the chemical and physical components of the etch/ash processes, which is useful in controlling damage in porous low-k integration. Independent control of the ion energy and plasma species enables the oxidation chemistry hybrid ash. The oxidation chemistry hybrid ash process not only effectively cleans the wafer, but also provides a CFX-free environment resulting in minimum chemical damage to the low-k structures. Independent control of the ion energy and plasma species also enables the optimal low-k feature shape in applications such as via-first dual-damascene low-k etching and ESL etching.

Acknowledgments

The authors would like to acknowledge the information concerning low-k/copper integration contributed by Dorel Toma and Eric Lee of Tokyo Electron America Inc. The authors are also thankful for the efforts of the process engineers of Tokyo Electron AT Ltd., who have contributed greatly to the experiments.

References

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Lee Chen received his PhD in applied physics from Columbia U. and is principal engineer at Tokyo Electron America (TEA), 2400 Grove Blvd., Austin, TX 78741; ph 512/424-1000, e-mail [email protected].

Hiromitsu Kambara received his MS in chemical engineering from Tokyo U. of Agriculture and Technology and is etch system marketing manager at TEA.

Masaaki Hagihara received his BS in chemistry and material science at Tokyo U. of Agriculture and Technology and is process development manager at Tokyo Electron Massachusetts LLC, Beverley, MA.

Akira Koshiishi received his MS in chemistry from Gakushuin U. and is a principal engineer in core technology development at Tokyo Electron AT Ltd. (TELAT) in Nirasaki City, Yamanashi, Japan.