Japan ramps up for high-volume SOI-based manufacturing
11/01/2005
The silicon-on-insulator (SOI) revolution that was first launched in Japan more than 25 years ago is returning home. A plethora of SOI-based applications, led by the IBM, Sony, and Toshiba breakthrough Cell processor, will launch new generations of high-end mobile and entertainment applications in the Asian marketplace. Sony itself has termed the applications enabled by its SOI-based Cell technology the beginning of a “paradigm shift in entertainment.” This and other developments worldwide prompted Gartner Dataquest last year to predict an SOI market of more than US$1 billion over the next five years, accounting for more than 10% of total silicon wafer sales.
In the beginning
SOI got its start in Japan in 1978, when Nippon Telegraph and Telephone Corp. (NTT) developed the separation-by-implanted-oxygen (SIMOX) process and gave the first demonstration of an SOI device. SIMOX technology was essentially the only viable SOI wafer technology until the early 1990s, when a practical wafer-bonding technology was invented. Mitsubishi announced the production of a low-power gate array on SOI in the fall of 1997 - just one year before the announcement by IBM. And Oki Electric has led the world by producing fully depleted SOI-based system-on-chip (SoC) LSI chips, which have been integrated into a very popular line of solar cell Casio watches for several years now.
The advantages of SOI are well established. By introducing a layer of insulation between the top face of the silicon wafer, on which the chips are fabricated, and the supporting base silicon, designers can create devices that are 30% faster and consume up to 50% less power than those made with traditional bulk silicon. The top active silicon layer in today’s SOI-based high-speed logic chips can be as thin as 500Å, which meets the needs of partially depleted devices down to the 90nm node. It is also suitable for low-voltage applications, such as chips for portable systems and communication devices, wireless applications, biomedical equipment, watches, game consoles, and so forth.
Next generation
With the next generation of ultrathin-film SOI for fully depleted high-speed logic devices at the 65nm node and beyond, the thickness of the top active silicon layer will get down to as little as 200Å (see figure). Solutions to the challenges of achieving high-volume production of these ultrathin layers (thickness uniformity, metrology, defect control, and surface nanotopography) are currently on track to meet the industry roadmap requirements.
 For the most advanced 300mm SOI wafers currently obtained using Smart Cut technology, thickness uniformity has reached to within ±10Å at 3σ. |
The Smart Cut [1, 2] technique for transferring ultrathin single-crystal layers of wafer substrate material (such as silicon) onto another surface uses an ion implantation and thermal activation process that acts as an “atomic scalpel” to slice the wafer horizontally, lift off a thin layer from the donor substrate, and place it onto a new substrate. A single donor substrate can be reused many times for further layer transfers. The bonding approach also extends beyond SOI to future technologies, including strained silicon-on-insulator (sSOI), FinFET, hybrid orientation technology (HOT), and the combination of silicon with other materials, including germanium, silicon carbide, and other III-V materials. Shin-Etsu Handotai, the world’s top wafer supplier, had the foresight to be prepared for this new generation. The company, as far back as 1997, became the first to license Soitec’s patented layer-transfer technology.
Leaders like Sony and Toshiba now recognize that SOI provides a long-term total cost advantage by providing a solution to the speed vs. heat dilemma. It is also now considered a tool for surmounting the “thermal wall,” the point at which scaling in bulk silicon leads to chips so hot they threaten the safety and reliability of the SoC.
The production of the Cell processor and its implementation in Sony’s next-generation PlayStation and related consumer electronics, home entertainment, and multimedia applications will undoubtedly mark a Japanese milestone in SOI. From the tremendous demands of digital content, scalable applications will emerge to serve both high-end applications, from digital televisions to home servers to supercomputers, and low-power applications, especially for mobile markets. In this sense, this year and the next will be very important for our industry. The ramp-up of Sony’s Nagasaki and Toshiba’s Oita 300mm fabs mark the launch of high-volume, SOI-based manufacturing in Japan.
This turning point will clearly affect suppliers. For example, Soitec, headquartered in France, recently created Soitec Asia in partnership with Seika Corp. Tokyo’s Soitec Asia provides SOI wafers and other engineered substrates to the Asian market. This will help meet demand for the most exigent service and support requirements on a local level. It also ensures that IC manufacturers in Japan and the Asia-Pacific region have access to SOI wafers and other engineered substrates as advanced technologies and device requirements emerge. The SOI revolution is upon us, and Japan is ready for it.
Acknowledgments
Smart Cut and Unibond are trademarks of S.O.I.TEC Silicon On Insulator Technologies. PlayStation is a registered trademark of Sony Corp.
References
- G.K. Celler, “Defined Film Thickness Leads to More MEMS on SOI,” Solid State Technology, Vol. 46, No. 12, p. 51, Dec. 2003.
- H.R. Huff, P.M. Zeitzoff, “SOI Wafers: Fabrication Techniques and Trends,” Solid State Technology, Vol. 47, No. 10, p. 30, Oct. 2004.
For more information, contact Makoto Yoshimi at Soitec Asia, Tokyo, Japan; ph 81/3-5221-7120, e-mail [email protected].
Pascal Mauberger, Soitec, Bernin, France, and Soitec Asia