Technology News
10/01/2005
STARC and Tohoku U. eliminate barrier layer from bottom of via
Taking a starkly different approach to the usual sputtered or ALD barrier layer that keeps copper from diffusing into the dielectric, Semiconductor Technology Academic Research Center (STARC) and Tohoku U. instead just add manganese to the Cu alloy used to fill the via hole. When heated, the Mn diffuses into the surrounding dielectric and reacts with oxygen there to form a layer of MnSixOy at the interface. But at the bottom of the via, where there is no dielectric and no oxygen with which to react, no barrier layer forms and only Cu remains. Once the MnSixOy interface starts to form, it limits further diffusion of the Mn into the dielectric, naturally limiting the barrier thickness to ~2nm.
Though thinner barrier layers usually mean more leakage, researchers say that the 2nm MnSixOy film has lower leakage than that of a conventional 15nm sputtered Ta barrier layer, with an electric field of 20MV/cm. By eliminating a barrier film where Cu meets Cu, via resistance is reduced to about half that of the conventional process. Adhesion between the Cu and the dielectric is also improved for better reliability. Work remains to be done on finding the best Mn density and an appropriate CMP process, so actual application may not be achieved until the 32nm node in 2010.
- SST partner Nikkei Microdevices
Nanotechnology news
LSI Logic to embed carbon nanotube memory in mainstream products
It looks like the first carbon nanotubes are about to show up in mainstream semiconductor products, and it turns out it won’t be any exotic new ultrahigh-end, high-performance application, but embedded memory on 0.18nm logic - driven by lower cost. LSI Logic reports that it plans to integrate Nantero’s carbon nanotube-based memory into its current-generation logic devices, using its existing tool set.
“For LSI, it’s a lower-cost solution,” says Verne Hornback, LSI Logic’s senior project manager, of the collaboration with Nantero. “We’ve fabricated a functioning NRAM with three layers aligned using our standard equipment set. We intend to use this technology in our existing G12 and Gflx [180 and 110nm] products, and our goal is to replace embedded SRAM at 90 and 65nm.” He notes the carbon nanotube development work has been running in parallel with CMOS manufacturing in the Gresham, OR, fab since 4Q03. Defense contractor BAE Systems, which has also completed qualification of the nanotube solution in its Virginia fab, is looking at radiation-hardened applications.
Nantero gets around the problem of aligning and connecting tiny single nanotubes by using instead a fabric webbing made of masses of tangled tubes, and a ribbon of the fabric to serve as a mechanical switch between electrodes, much like the mechanical relays in the first computers. An array pattern of ribbons of nanotube webbing can thus be formed across the chip, suspended over interconnect trenches, explains Avo Kanadjian, Nantero’s VP of business development. Sending a charge through the ribbon makes it sag down into the trenches to contact the electrodes. When the power is removed, Van der Waals forces maintain the ribbon in its flexed state, where it conveniently consumes no power, since there’s nothing to leak.
Key to making the material usable in a fab is filtering out the carbon nanotubes’ typical 5% iron content down to <25ppb metal contaminates, and developing a solvent for the nanotube solution that can be spin-coated in a monolayer at room temperature, then patterned by standard photolithography, dry etch, and solvent strip.
Hornback says once they showed that the materials could be used on the same equipment without contamination issues, with procedures for checking for backside clean, edge clean, and cleanup after breakage, designers got enthused about the prospects of integrating potentially large-capacity, low-power, nonvolatile memory onto the back end of the logic process, since it allows them to decide where to add memory late in the flow, and to avoid putting any memory on the slice, leaving more room for other functions.
“We need help on inline defect inspection,” Hornback adds, “since the nanotubes look like defects.” - P.D.
Startups aim nanotechnology processes at enhanced resist coating, sensors, interconnects
Proposing an alternative to spin-coating for polymer resists or dielectrics down to 1nm layers, Nanometrix, a five-person startup in Montreal, has devised a novel technique that floats a layer of coating material on water, then slides it over the substrate. The process could potentially apply photoresist without striations or edge bead - and with no wasted material. “We sent a sample to an IC company with a 5.7nm layer and 0.2nm-0.3nm roughness, using the standard DUV resist they sent us in a black bottle,” says Patrick O’Connor, GM. The company is just starting to look at coating patterned wafers, but it appears the process can evenly coat topography as well.
The process flows water down a ramp, then gently applies the desired coating material to the surface of the water. The liquid flows into a trough, where the coating material forms a monolayer on top of the water (see figure). The wafer is then brought up through the monolayer.
 Nanometrix proposes alternative to spin-coating resist. |
Varying the quantity and injection speed of the coating material controls the thickness and uniformity of the coating, from 1-300nm thick, with smoothness from 0.1-1.0nm. The venture turned the relatively well-known laboratory technique into volume production that runs a 12-in. wide strip of material through the process at a meter per minute. Though initially aimed at coating flexible substrates, the process has actually found most initial interest from Mattel, for making fancier material for Barbie dresses. Resist coating looks like the easiest electronics application to tackle, since the material itself doesn’t need development work, and it doesn’t stay on the wafer. But some potential users are also looking at low-k and high-k dielectrics.
O’Connor says the company has been running its beta machine and is raising money to build a commercial unit for wafers.
Starting to develop actual early prototype devices with its self-assembly process for nanoclusters is Nano Cluster Devices, Christchurch, New Zealand. The company is showing a hydrogen sensor that uses tiny nanocluster wire to get very quick reaction time, and it has a new deal with SiliconPipe of San Jose to use the technology to make high-speed copper clip-on interconnects between chips. Nano Cluster executive director Simon Brown explains the technology for making the wires: “It’s like dropping ball bearings into a V-shaped valley. They all roll to the bottom.” He notes that the company uses fairly conventional thermal evaporation and sputtering to make its clusters of common electronic materials, as well as standard lithography, lining up the nanoclusters at the bottom of the groove to make its wires 100× smaller than the lithography node. The clusters are then fused by passing a current through them. “After deposit, the ability to control the amount of sintering of the clusters is really important,” says Brown, noting that the clusters need to be highly sintered for electronic circuits, but more granular for gas sensors.
NanoDynamics, meanwhile, is making uniform metal powders with particles as small as 10nm with a high yield process that brings down costs. Instead of the usual melt and spray method, the 60-person Buffalo, NY, company precipitates the metal powders, using technology from Clarkson U. and some basic, control-everything chemical engineering that allows crystallization to all occur at the same time, so the particles are all the same size.
The key is to coat the surface of the highly reactive particles with a monolayer of polymer to keep them from reacting and clumping together. With its low reactivity, the metal powder can be applied in adhesive at under 200°C for inkjet-printed circuits, or used in bumps or other types of chip interconnections. It also could potentially be used in low melting-point solders. - P.D.
‘Electro Pen’ may impact developing nanotechnologies
A new chemical writing technique that can create lines of “ink” only a few nanometers wide has been developed by scientists at the US Dept. of Energy’s Brookhaven National Lab.
“Our new ‘writing’ method opens up many new possibilities for creating nanoscale patterns and features on surfaces,” says Brookhaven Lab physicist Yuguang Cai in a recent news release. “This may have a significant impact on developing nanotechnologies that involve nanopatterning, such as molecular electronics: tiny circuits built using single organic molecules.”
The new technique, electro pen nanolithography (EPN), involves sweeping a thin metal tip across a film of organic molecules. The tip carries an electric voltage that causes the region under it to oxidize. In a single sweep, organic “ink” molecules are transferred from the tip to the oxidized areas, creating an extremely thin line.
Each line is just one molecule thick, but the researchers can produce multilayered patterns by writing over the existing pattern, making them able to create 3D nanoscale “landscapes.” By turning off the voltage, they can also use the tip as a tiny scanner to read and create an image of the pattern just written. With further research, EPN may have the ability to “write” biomolecular materials, such as proteins, onto surfaces.
New ways to make cavities within wafers may reduce MEMS costs
Robert Bosche GmbH and Hitachi Ltd. are each reporting radically new approaches to making the covered cavities in silicon needed for MEMS pressure sensors and other applications, eliminating the high cost of etching out a deep area and attaching a glass cover, and allowing supporting CMOS circuitry to be made directly on the MEMS structure.
Bosche uses porous silicon, inset in areas of the silicon wafer’s surface, then tops it with a layer of epitaxial silicon (≤10μm), and anneals it at 1000°C. The high heat collapses the arrangement of silicon atoms, leaving a near vacuum cavity under a membrane surface. Regular CMOS circuits can then be made on the epi layer by standard processes. Bosche figures it will make low-cost consumer products such as automotive sensors and film acoustic resonators for cell phones using the process within a year or two.
Hitachi Ltd.’s central research laboratory, meanwhile, reports similar results with a quite different approach, using only standard CMOS materials and processes to create its covered cavity. It covers the TEOS layer with a tungsten mask, then makes small etch holes in the mask over the region to become the cavity. An application of HF enters the holes, etching out the desired cavity. An SiN/SiO CVD layer over the top then covers up the holes, closing off the cavity, and standard CMOS circuit production can continue.
- SST partner Nikkei Microdevices