The challenges of adjusting scaling control knobs
10/01/2005
In 1965, Gordon Moore first observed an exponential growth in the number of transistors per IC and devised a law that threw down a gauntlet and, through intense competition, has enabled amazing gains in chip performance. However, all exponential laws must reach a limit. If the number of transistors continues to double unabated, either chips would eventually be larger than the earth, or transistors would be smaller than the subatomic particles of which they are made.
Moore’s Law is yet another technological “S” curve in the history of mankind. In the beginning, there is exponential growth followed by an inflection in which the law of diminishing returns begins to dominate. Even with the law being limited by physics, the number of transistors per IC is nearing the one billion mark. This march toward a billion-transistor chip has led to shrinking (or more properly termed, scaling) of today’s transistors to nearly 20nm.
If we examine the equation of transistor drive current - a key predictor of circuit speed - it’s clear that there are more “knobs” to turn in the drive for speed. However, as the transistor density increases, power consumption rises, posing a severe challenge to the continuous scaling of high-speed chips. The paths that have been taken and are currently underway to achieve “fast and cool” ICs are reviewed.
The physics of speed
At the simplest level, the speed of CMOS-based ICs is determined by the amount of current that can flow through individual transistors. The classic equation relating the maximum amount of current - the saturation current - is expressed as:
where Idsat = saturation drive current, μ = carrier mobility, L = channel length, ε = gate dielectric constant, W = channel width, ε0 = universal dielectric constant, Vcc = power supply voltage, tox = gate dielectric thickness, and Vt = threshold voltage.
Transistor designers treat each of these parameters as a knob to dial in the desired performance (Fig. 1): maximum saturation current with minimum off-state leakage current.
 Figure 1. Control knobs available to device designers to maximize Idsat. |
Channel length (L). Historically, device scaling was dominated by turning down the L knob. When scaling L, vertical dimensions within the silicon must also be reduced in order to suppress short channel effects (SCE) (i.e., a transistor’s ability to be turned off). Methods of producing ultrashallow source-drain extension junctions have been developed, including lowering the implant energy, utilizing novel co-implant species to control dopant diffusion, and reducing the activation thermal budget. Newer doping technologies such as plasma doping and atomic-layer deposition have also emerged as promising alternatives to conventional doping methods in answering the need for ultrashallow, diffusionless, and well-activated junctions.
Gate dielectric: thickness (tox) and dielectric constant (ε). The electrical properties of the gate dielectric are additional knobs to achieve device scaling goals. Because device drive current is inversely proportional to the gate dielectric thickness, a reduction in the equivalent oxide thickness (EOT) ensures an increase in drive current. When the operating voltage of the device is reduced, EOT must be thinned accordingly to maintain the same inversion layer charge in the Si channel. Thinner dielectrics, however, lead to higher leakage currents due to tunneling of charge through the gate. High-k dielectrics such as HfO2 and ZrO2 with interfacial layers are under investigation as replacements for nitrided SiO2. One of the challenges with integrating high-k dielectrics is the Fermi level pinning exhibited in the high-k/poly Si gate stack that leads to higher threshold voltages. Using metal gates to replace poly Si gate is a viable approach to maintain lower threshold voltages. Metal gates also have the advantage of minimizing poly depletion, which reduces the apparent EOT of the gate stack, thereby giving another boost to drive current.
Carrier mobility (μ). The hottest area of semiconductor materials research in the past few years has been improvement in carrier mobility. The primary method for increasing μ has been the introduction of strained silicon in the channel. Carrier mobility in silicon under uniaxial strain is being employed to further enhance device drive current. The strained lattice is accomplished differently for n- and p-channel devices. A Si3N4 tensile strained layer is used for nMOSFETs and a recessed etch flowed by selective epi of SiGe is used for compressive strain of pMOSFETs. These new integration schemes are extending the use of current materials and delaying the inherent complexities of introducing new materials such as Ge and GaAs.
The problem of power
As device drive current increases, power dissipation becomes a major concern. The process control knobs described are used to increase drive current. The next goal is to conserve as much of this newly created current as possible. As junction depth shrinks, the electrical current going from source to drain encounters higher resistance. To minimize this resistance, an elevated source drain thickens the junction area through a selective epitaxial process without degrading SCEs. Lower resistances from elevated source drains keep the current from being turned into heat.Silicon-on-insulator (SOI) places the junction area on top of a dielectric layer so junction capacitance is effectively minimized and less current is needed to switch the transistor.The transistor is therefore operated more quickly with less power consumption. Another major benefit of SOI technology is the reduction of soft error rate, a growing issue as ICs scale. In its optimal state, SOI would have the surface silicon layer thinner than the channel depletion layer (i.e., fully depleted SOI), which leads to the process challenge of making the silicon layer thickness highly uniform. Combining SOI with the scaling knobs already discussed would yield the fastest and coolest chips yet.
Conservation of space
The “planar” bulk silicon CMOS process with its new materials and integration schemes using the scaling knobs of μ, ε, tox, and L will continue to yield performance improvements. However, one knob exists that, to date, has not made its way to mainstream ICs - the width of the device, the W knob. W can be used if you “fold” the transistor, meaning to go up rather than spreading out, saving valuable silicon real estate (Fig. 2). Multigate FETs (MuGFET) would increase drive current per unit area while suppressing SCEs. The main process challenge for making MuGFET devices is the conformal doping of 3D structures. Continued scaling of 3D FETs would be achieved by increasing the height of the fin, yet this would exacerbate the conformal doping challenge.
 Figure 2. FinFETs enable device designers to add gate width as a control knob. |
Finally, in the era of nanotechnology, tremendous effort has been spent in search of revolutionary materials for future CMOS devices. Carbon nanotubes (CNT) are one of the most widely investigated options. CNTs are long, single- or multiwalled cylinders of carbon atoms with unique electrical and mechanical properties. CNTFETs are transistors that employ CNTs as the channel of the FET and exhibit high carrier mobility, flexibility with gate dielectrics, and no demand for high thermal budget. CNTs would enable continued scaling, but at the expense of trading in the well understood silicon infrastructure.
It is clear that Moore’s Law has inspired technologists, but the inflection point of scaling has been reached. The “S” curve is flattening and modest performance gains require increasingly more complex process schemes. Competition will demand that scientists and engineers continue to squeeze performance from devices. Until the next “S” curve is in play and there is a new exponential law - e.g., photonics, quantum computing, etc. - adjusting the scaling knobs and managing their impact on power and space will continue to be the main challenges.
Peter Nunan received his MSEE in semiconductor device theory and fabrication techniques and his BS in engineering physics in semiconductor theory and applications from Lehigh U., Bethlehem, PA. He is VP of technology development at Varian Semiconductor Equipment Associates Inc., 35 Dory Rd., Gloucester, MA 01930; ph 978/282-2437, e-mail [email protected].
Further reading...
SST editors recommend these other articles on the challenges and consequences facing transistor scaling, available at www.solid-state.com:
- Victor Moroz, Dipankar Pramanik, Francois Henley, Philip Ong, “Options at the 45nm Node Include Engineered Substrates,” Solid State Technology, July 2005.
- T.M. Parrill, L.M. Rubin, “Transistor Scaling is Moving Implant Energies Lower,” Solid State Technology, June 2005.
- Peter M. Zeitzoff, “Transistor Scaling Progresses, but New Challenges Loom,” part of “ITRS Special Report,” Solid State Technology, January 2005.