A 90nm wafer-level technique for thin-film stress monitoring
10/01/2005
Coherent gradient sensing (CGS) is an emerging thin-film stress metrology technique that provides a method to map wafer-level stress on both blanket and patterned films. The technique was evaluated at Intel to assess wafer stress concentration at the 90nm technology node and demonstrated high image resolution, patterned wafer capability, and high measurement throughput. Results were correlated to electrical and mechanical reliability data, and agreed with learning from 130nm technology development.
Conventional wafer film-stress measurement utilizes stress monitoring equipment that makes measurements along the diameter of an unpatterned monitor wafer to determine the wafer curvature and calculate stress. Since limited data are used to calculate wafer curvature, only average film stress can be extracted using such a method. As a result, any local stress concentrations will be missed, especially at critical locations along the wafer edges. Other disadvantages of this technology are its sensitivity to vibration, low measurement throughput, and inability to measure patterned wafers.
In recent years, IC packing density has steadily followed Moore’s Law. The increase of IC device density combined with increased wafer size and process complexity was predicted to change the wafer deformation from spherical to saddle-like distortion (Fig. 1a) [1]. The prediction of complex distortion states has been confirmed using CGS whole-wafer curvature mapping technology on 300mm wafers (Fig. 1b).
CGS principle
The CGS method is a full-field, interferometric technique that was developed by Rosakis et al. at the California Institute of Technology for curvature measurement in thin-film applications [2]. Figure 2 shows a schematic illustration of the CGS set-up in the reflection mode. In this mode, two gratings are used to shear a collimated laser beam that is directed to and reflected from a silicon wafer with various thin films. Because the shearing process produces fringes that are contours of constant surface slope, two orthogonal sets of interferograms must be acquired to fully characterize the deformation. Examples of orthogonal x and y inteferograms are also shown in Fig. 2.
 Figure 2. CGS interferometer schematic and interferograms. |
The nonuniform stress in the film will result in local wafer curvature variation. The local variation is expressed in terms of a curvature tensor field, which is determined from the CGS patterns recorded in reflection mode by differentiating the fringes of the in-plane gradient. The film stress is then calculated using Blake’s Equation.
CGS offers several advantages. It provides full-field information on the whole wafer as well as at the die level. The data acquisition is extremely fast, typically a fraction of a second. The measurement can be done on patterned wafers. And, since CGS technology measures gradients of displacement rather than displacement itself, no special provisions are necessary to isolate the system from vibration. These advantages, coupled with high throughput, make CGS film-stress technology an attractive option for high-volume manufacturing as well as process diagnostic and development activities.
Experimental procedure
Two experiments were designed and executed for CGS technology evaluation in C4 UBM (controlled-collapse chip connection, under bump metallization) applications. In Experiment 1, 6000Å of unpatterned monitor wafers (6K OX) and patterned test wafers (called MCY) were used. The objective of this experiment was to evaluate CGS technology for C4 applications. The wafers were processed at Intel, and CGS stress was measured at Oraxion Diagnostics. Experiment 1 wafer process conditions are listed in Table 1.
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In Experiment 2, a more comprehensive test matrix was laid out. The objectives of this experiment were to confirm the results of Experiment 1, to assess stress evolution through the C4 operations, and to attempt a correlation between CGS film stress and electrical and mechanical reliability data. One set of 6K OX monitor wafers and two types of patterned test wafers (MCY and TV1) were used for film stress evaluation at interim C4 operation steps: UBM deposition, UBM etch, and C4 bump reflow. After C4 operations, one set of wafers was subjected to a bump-pull test for UBM adhesion evaluation in a detailed test procedure [3]. The wafer process flows are listed in Table 2.
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Results and discussion
Figure 3 shows a series of CGS stress maps comparing results obtained on patterned and monitor wafers. The MCY and the monitor wafers were processed under identical UBM deposition conditions. The stresses were mapped using levels ranging from +150 to -150MPa: the average and rms stresses are given directly below each stress map. When deposited under a no-cooling condition, the monitor wafers showed about half of the tensile stress levels seen on the patterned wafers. When deposited under the cooling condition, the stress of the patterned wafers changed to slightly compressive, while the stress of the monitor wafers showed no difference. These data demonstrated that the monitor wafers are not equivalent to a product wafer for film stress. Therefore, the current monitor wafer will not capture UBM process excursions associated with film stress issues.
 Figure 3. CGS wafer stress maps of a) a patterned MCY wafer and b) a monitor wafer. |
Figure 4 shows CGS wafer-stress maps of TV1 wafers under different UBM deposition conditions: UBM1, UBM1 Improve, and UBM2. Comparison of the maps reveals that UBM2 is under a uniform tensile stress, and UBM1 Improve wafer stress is less uniform and slightly compressive, whereas the UBM1 wafer is highly nonuniform with a high compressive stress. It is interesting to note that a wafer edge-stress concentration is present in the UBM1 wafer film-stress map. This concentration makes the bumps at the wafer edge more susceptible to UBM delamination. The wafer edge-stress concentration cannot be detected by conventional technology due to nonuniform stress distribution.
 Figure 4. CGS wafer stress maps showing process impact. |
Figure 5a shows a series of CGS stress maps from one group of MCY wafers taken after UBM deposition, UBM etch, and the bump reflow operation from an old C4 process. The stress maps reveal that a nonuniform film stress developed after UBM deposition. The wafer edge-stress concentration is clearly exacerbated by the etch operation. Bump reflow annealed out the film stress nonuniformity, but the UBM adhesion was reduced at the wafer’s edge. During the 130nm technology development, wafers with UBM delamination were associated with an “ear” signature of electrical sort failure (Fig. 5b). The correlation between the CGS stress and the sort failure signature suggests that the CGS stress map at the relevant process step can be used as an indicator of UBM delamination. UBM delamination and adhesion were well-characterized and correlated in a separate bump-pull test [3].
 Figure 5. Wafer stress maps showing correlation between a) CGS stress and b) electrical sort failure. (BLM is an Intel process for UBM layer deposition.) |
Figure 6 shows work at Sematech where CGS technology was applied to a two metal-layer, dual-damascene process on 300mm wafers [4]. The wafer stress was measured at 13 interim operations through the process. The cumulative film stress was plotted and showed two distinct features. The first one is that wafer stress increased ~100MPa on the tension side from Metal 1 to Metal 2 operations. At the 90nm technology node, a logic device typically has seven to eight metal layers. With this trend, the overall film stress increase could be in the range of hundreds of megapascals at the last metal layer. The other feature is the stress spike and sharp drop after copper electroplating and after anneal, respectively. This was the first demonstration that the wafer stress can be measured and used for process characterization, diagnostic, and improvement efforts. Other CGS technology applications can be found in [5].
 Figure 6. Cumulative wafer stress through Metal 1-Metal 2 operation steps. |
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Conclusion
Monitor vs. patterned wafer comparison data revealed that conventional thin-film stress metrology cannot identify local film stress variations or measure stress on patterned wafers, and has very limited capability to catch UBM excursions. Wafer-level stress data confirmed that at the 90nm technology node, the wafer stress distribution (of 300mm wafers) has already moved from the spherical to the multimode region due to wafer size and process complexity. In the multimode region, stress is more concentrated at the wafer’s edge, which results in a higher probability of UBM excursion due to film delamination.
CGS examination of wafer stress evolution through C4 operations provided an understanding of the UBM development and improvement at Intel’s 130nm and 90nm technology nodes. CGS wafer stress results were correlated to electrical sort data and mechanical bump-pull data for UBM reliability assessment. CGS technology was also demonstrated by Sematech and Oraxion in backend wafer-fab processes.
CGS technology, with high-resolution stress mapping and patterned wafer capability, presents a technology for true film-stress in-line monitoring in a high-volume manufacturing environment and for process development applications.
Acknowledgments
The authors thank Jerome Lazarczyk and Jonathan Arndt for their support of process integration, assembly, and reliability tests; Jorge Valadez and Caroline Merrill for bump-pull tests; Fab 11X C4 process engineers and technicians for experiment execution; Oraxion Diagnostics for CGS stress measurement support and permission to use the data; Ronald Carpio for Sematech application discussion and permission to use the data; and Bob Deysher for technical review of the manuscript. The CGS measurement technique is a trademark of Oraxion Diagnostics.
References
- H. Lee, A.J. Rosakis, L.B. Freund, “Full-field Optical Measurement of Curvatures in Ultra-thin-film-substrate Systems in The Range of Geometrically Nonlinear Deformation,” J. Appl. Phys., Vol. 89, No. 11, pp. 6116-6129, June 1, 2001.
- A.J. Rosakis, R.P. Singh, Y. Tsuji, R. Kolawa, N.R. Moore Jr., “Full-field Measurements of Curvature Using Coherent Gradient Sensing: Application to Thin Film Characterization,” Thin Solid Films 325, pp. 42-54, 1998.
- J. Li, et al., “Bump Pull Test for Excursion Prevention due to C4 UBM Delamination,” NMTeC 2004, Oct. 2004.
- C. Boye, R. Carpio, J. Woodring, “A New Optical Technique for Monitoring Wafer Curvature and Stress During Copper Damascene Processing,” 29th SPIE Symp., Feb. 2004.
- R. Carpio, S. Dorris, J. Woodring, J.D. Owen, D. Abisia, “An Investigation of the Effects of Wafer Curvature Changes During Copper Damascene Processing,” ECS 205th Meeting, May 2004.
For more information, contact Jianxing Li, senior staff technologist, at Intel Corp., 4100 Sara Rd., Rio Rancho, NM 87124; ph 505/794-8484, e-mail [email protected].
Marvin Partin, Raymond Carey, Avi Fuerst, William Johannes, Mahalingam Sankararaman, Intel Corp., Rio Rancho, New Mexico