Using multiple transducers at sub-65nm for single-wafer megasonics-based cleaning
10/01/2005
Wafer cleaning has traditionally relied on the combination of strong chemistries and high-power megasonic energy to achieve cleaning efficiencies >90%. With new 65nm processes now moving into the preproduction phase and 45nm technologies in R&D, a major roadblock has emerged. Cleaning engineers face the conflicting challenges of achieving high particle-removal efficiency (PRE) with no megasonics-induced damage to fragile device structures and ultrastringent limits for material loss (i.e., oxide and Si consumption). This article reviews megasonic cleaning hurdles and describes results from a novel three-transducer approach to single-wafer cleaning in 65nm and 45nm processes.
The increasing process complexity and the introduction of new materials at the 65nm technology node have given rise to a greater number of total processing steps, which have required a corresponding increase in the number of cleaning steps to maintain yields. For example, the percentage of wafer cleaning steps for a DRAM process flow has increased from 40% of the total process steps at the 160nm technology node to almost 70% at the 65nm node [1]. This increase in cleaning steps is compounded with more demanding process requirements, including preventing cross-contamination associated with new materials, processing smaller feature sizes with higher aspect ratios, and cleaning without damaging sensitive device structures.
The cleaning dilemma
Along with the increase in wafer cleaning steps, the requirements for wafer cleaning have increased to new levels, as documented in the International Technology Roadmap for Semiconductors (ITRS) [2]. Of particular note are the sub-angstrom film consumption requirements and the rapid shrinking of killer defect particle size to well below 50nm dia. These requirements in sum present a cleaning dilemma.
At the core of the cleaning dilemma is the reduced efficiency of removing sub-50nm particles. The challenge in removing these nanoparticles is that the ratio of the particle removal force to the particle adhesion force decreases dramatically with the shrinking particle diameter. In particular, the removal force ratio for the megasonic forces drops off as 1/d2. Clearly this presents a major challenge for megasonics-based cleaning of smaller-diameter particles.
In order to compensate for the reduced megasonics PRE, the conventional options are to 1) increase the megasonic power level, and/or 2) increase the concentration of Standard Clean 1 (SC1) chemistry concentration, time, and/or temperature. Unfortunately, neither of these options is feasible for the more demanding 65nm surface preparation requirements. Option 1 introduces an excessive level of megasonic damage to smaller geometries, and option 2 increases film consumption to intolerable levels.
In general, there is a linear increase in megasonic damage with increasing PRE. A recent study of the relationship between megasonic damage and PRE for multiple cleaning tools concluded that no tool (batch or single-wafer) was capable of achieving the target of high PRE without damage [3]. Batch megasonics typically cause extensive damage to sensitive device structures, owing to poor control over the megasonic energy distribution. Single-wafer tools offer improved control, but still exhibit isolated damage to sub-90nm structures.
While poor cleaning efficiency will have a direct effect on fab line yields, the device effects caused by cleaning-induced film loss during gate stack formation are less obvious. These can include an increased isolation leakage current, a shorter effective channel length, and increased source/drain resistance.
An additional surface preparation challenge presented at the 65nm node is the introduction of new materials, particularly in the device gate stack. These present stringent requirements for a native oxide-free surface without particle defects. Unfortunately, this presents an additional dilemma since the HF-last cleans, which remove native oxides, are notorious for leaving high particle counts, especially in batch tools.
Single-wafer surface preparation
The cleaning dilemma presented at the 65nm technology node is driving the industry to single-wafer processing for most surface preparation steps. Batch tools have proven incapable of achieving high PRE without megasonic damage, watermarks, and film consumption. Furthermore, particle addition with HF-last cleans in batch tools is well above the levels that can be achieved in a single-wafer tool [4]. Single-wafer cleaning tools offer more precision in terms of megasonic energy distribution and flow uniformity.
 Figure 1. Ideal megasonics energy distribution required for effective particle removal without structure damage. |
In order to use megasonics in wafer cleaning, the megasonic energy distribution at the wafer surface must be precisely tailored to be above the threshold required for particle removal, yet below the value that causes structural damage. Figure 1 shows a representation of the ideal energy distribution. As study by IMEC demonstrated, no tool to date has been able to realize this ideal megasonic energy distribution [3].
Megasonic cavitation and sonoluminescence
Megasonic energy applied to a cleaning solution produces acoustic phenomena generally known as cavitation. Cavitation phenomena include gas bubble oscillation and implosion, and acoustic streaming, which is a megasonics-induced convective flow. The bubble cavitation cycle is generally thought to be the primary cleaning mechanism in megasonic cleaning systems. One technique that has recently been developed to characterize bubble cavitation in wafer cleaning processes is sonoluminescence [5].
Sonoluminescence refers to the photon emission that occurs when a collapsing cavitation bubble heats the gas within to temperatures that are high enough to generate incandescent light. Many studies using sonoluminescence to measure megasonics-induced cavitation have indicated that the single-transducer arrangement used in a batch tool cannot realize the degree of control required to tailor the energy distribution for 65nm and beyond processes [3]. This has led many researchers to investigate alternate megasonic technologies that are possible with a single-wafer system.
Multiple megasonic transducers
One new approach to single-wafer cleaning, incorporated in the Applied Materials Emersion processor, uses an immersion-style chamber and a configuration of three megasonic transducers (Fig. 2). The combined megasonic energy from these transducers is focused at the three-phase interface of wafer/liquid/air. Exposure of the entire wafer surface allows multiple acoustic wavefronts to be applied to the wafer. The wafer is swept up and down multiple times during cleaning in order to expose the entire wafer surface to the three-phase interface. The wafer sweep cycle through megasonic wavefronts is depicted by the up/down arrows showing wafer motion past the upper transducers in Fig. 2.
The exposure time of any die on the wafer to the megasonic power during a 20-30 sec cleaning process is limited to milliseconds, thereby minimizing damage. The combined action of the wavefronts and the sweep cycles allows reduced megasonic power levels and reduced process times, which prevent damage without sacrificing cleaning.
Figure 3 shows a plot of the megasonic damage on 65nm poly-Si structures vs. PRE for single- and multiple-transducer configurations. In a triple-transducer chamber, a PRE value of >90% can be achieved without damage to 65nm structures. The combined interaction of the acoustic energy fields from the three transducers and the sweep of the entire wafer through the three-phase interface creates an energy distribution much like that represented in Fig. 1. The importance of the transducer interaction is demonstrated in Fig. 4, which shows the PRE response surface with various combinations of the transducers. The ternary plot shows a well-defined center region where high PRE values are realized. This region corresponds to the case where all three transducers are used during cleaning. Many of the data points within this region were achieved using extremely low megasonic power levels on the multiple transducers (e.g., <0.2W/cm2). The PRE drops off dramatically at each apex where a single transducer is used.
The ability to achieve PRE values of >95% using a dilute SC1 solution with a process time of <30 sec is highly unusual. This short process time combined with the dilute chemistry does not allow for sufficient etching to undercut and lift adsorbed particles. Therefore, the transducer interactions are the primary cleaning mechanism, with the high PRE values driven only by the megasonic configuration. This multiple-transducer approach allows for a solution to the sub-65nm cleaning dilemma. The short SC1 process times with dilute concentrations limit film consumption to the subangstrom levels required by the ITRS. The typical oxide loss during an SC1 clean is <0.3Å, compared to 3-6Å for a batch tool (see table). This value meets the ITRS target, which has been identified as a red brick wall for the sub-65nm technology nodes.
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Sonoluminescence testing and results
The PRE results described previously indicate that some unusual acoustic effects are occurring in the cleaning chamber. In order to provide a direct indication of these phenomena, sonoluminescence imaging was performed. In these tests, an optical imaging system was mounted on top of the chamber to measure sonoluminescence within the chamber [6]. Sonoluminescence profiles for multiple combinations of transducer configuration and power levels are summarized in Fig. 5. This curve shows the photon intensity profile along the axis between the two transducers, with the wafer front surface located at x ≈-0.04cm. The notation for the power densities is “bottom/front/back.” The flat line curve with the bottom transducer acting alone demonstrates that very little cavitation is produced with the bottom transducer operating at low powers (similar to a batch tool when attempting to avoid damage). However, the low-power condition with all three transducers firing at 0.2W/cm2 showed a very uniform cavitation profile.
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PRE, sonoluminescence, and damage
Figure 6 shows a plot of the 65nm structure damage and PRE vs. sonoluminescence. This plot demonstrates that it is indeed possible to achieve the target value of >90% PRE without damage to 65nm device structures. As previously discussed, the secret to this success is the ability to precisely tailor the megasonic energy distribution with the use of multiple interacting transducers. The plot clearly demonstrates a threshold sonoluminescence value at which structure damage occurs. These results show that the PRE can reach >90% while operating below the damage threshold. This large process window represents the realization of the energy distribution depicted in Fig. 1. Damage-free cleaning has been shown on both 50nm and 65nm poly-Si lines with a corresponding PRE value of >90%.
These results can be combined to formulate a theory of operation for the multiple transducers in the system’s chamber. Sonoluminescence data shows that any individual transducer acting alone at low power produces very little cavitation, and therefore a very low PRE value (typically <50%). However, when three transducers are employed simultaneously, a high PRE can be achieved while still keeping the cavitation levels below the threshold for structure damage. The interactions of the multiple transducers, combined with the wafer sweep, allow the creation of a uniform energy distribution and controlled bubble cavitation events at the wafer surface.
The close proximity of the front and back transducers, which are incident at an oblique angle to the device and back sides of the wafer, concentrate the megasonic energy at the wafer/fluid/air interface. The wafer travels through this interface during sweeps. This three-phase interface concentrates the acoustic fields. The optimized sweep rate enhances particle removal but limits the exposure time of any individual wafer die to milliseconds to avoid device damage.
The sonoluminescence results indicate that much of the improvement in PRE with multiple transducers is due to cavitation from the back transducer. Since there are no direct acoustic effects acting on the wafer frontside from this transducer, this suggests that Lamb waves created on the wafer surface are contributing to the cleaning process. These surface vibrational states introduce additional cleaning mechanisms at low power levels, particularly when acting in combination with the traditional hydrodynamic, rolling moment, and acoustic streaming removal mechanisms [7]. These additional forces enable cleaning at low cavitation levels without causing damage [6].
Conclusion
The 65nm technology node has introduced a series of daunting wafer-cleaning challenges with conflicting solutions. These include achieving high PRE (>90%), cleaning without megasonics-induced damage to fragile device structures, and ultrastringent limits for material loss (sub-angstrom oxide and Si consumption). Traditional batch cleaning systems have not resolved this cleaning dilemma. Single-wafer cleaning tools may improve cleaning capabilities, but challenges still exist in using traditional megasonic designs in surface preparation applications. A novel three-megasonic transducer architecture has shown a PRE of >90% without damage to sub-65nm structures, promising damage-free cleaning in next-generation processes.
Acknowledgment
Emersion is a registered trademark of Applied Materials Inc.
References
- G. Kim, et al., Proc. 7th Intl. Symp. on Ultra Clean Processing of Silicon Surfaces, pp. 67-70, 2004.
- International Technology Roadmap for Semiconductors, International Sematech Publications, Austin, TX, 2004.
- G. Vereeke, Proc. 7th Intl. Symp. on Ultra Clean Processing of Silicon Surfaces, pp. 141-146, 2004.
- J. Rosato, Semiconductor Manufacturing, Vol. 5, No. 5, pp. 70-78, 2004.
- G. Ferrell, et al., J. Acoust. Soc. Am., Vol. 112, No. 3, Pt. 1, 2002.
- F. Zhang, et al., J. Electron. Mater., Vol. 29, No. 2, pp. 199-204, 2000.
- J. Rosato, et al., Proc. 6th Intl. Symp. on Ultra Clean Processing of Silicon Surfaces, pp. 45-48, 2002.
For more information, contact John J. Rosato at Applied Materials Inc., 255 Steelhead Way, Boise, ID 83704; ph 208/685-3236, e-mail [email protected].
M. Rao Yalamanchili, Applied Materials Inc., Boise, Idaho