Technology News
09/01/2005
Applied seeks advanced transistor applications with conductor etch tool
The latest etch technology from Applied Materials, called AdvantEdge, targets 45nm and 32nm applications such as high-k dielectric/metal gate and 3D transistor architectures. The new process builds on the company’s DPS etch system and DPS II process technology.
Thorsten Lill, GM, Conductor Etch Division, says the tool has a wide process window due to multiple process tuning knobs that optimize the gas injection profile across the wafer, match temperature across the wafer to the optimized gas injection profile, and tune the ion flux. The former two capabilities drive CD performance in polysilicon etch while the latter drives the etch rate.
CD performance has been pushed to the wafer’s edge by keeping the deposition rate of the reaction by-products to the profile sidewall constant across the wafer, according to the company, in effect tuning the sticking coefficient. “Extending CD performance to the edge - with a 2mm edge exclusion - equates to a 7.7% gain in available real estate,” said Lill, adding the process has a <3nm CD uniformity.
Applied is targeting the new process for strain engineering at the 65nm node (e.g., for SOI, SiGe and Si:C, and strained PECVD spacers). At 45nm, applications include strained silicon with new materials for high-k and metal gates. At 32nm, the tool could be used for 3D structures such as FinFETs and tri-gate transistors. Also, the company has data from Yoshio Nishi of Stanford U. that shows NAND flash density is increasing every two years, so Applied is eyeing NAND flash development at 32Gbit densities. - D.V.
45nm opportunity: Hopefuls propose new ways to measure new things
Virtually everything may be up for change at the 45nm node, but it looks like the metrology space may be the center of the action, judging from the frenzy of new players proposing new ways to measure new things at this year’s Technology Innovation Showcase at Semicon West.
Bede Scientific, Durham, England, looks to bring x-ray detection of crystallographic defects within the wafer from the lab into the fab, and expand its usage from inspecting incoming blank wafers to finding where processing is causing defects. The company’s new x-ray tool has gone digital, eliminating the need for film, allowing automation, and speeding analysis. Instead of using a point detector, Bede uses a CCD detector that can integrate all the single frames. As well as the usual reflection mode, with the detector on the same side of the wafer as the source, it uses transmission mode, with the detector on the backside of the wafer, so the tool sees all the way through the wafer. These changes allow the tool to identify more precisely just where and what the structural defects are. Critical applications could be checking SiGe relaxation, or measuring layer thickness as layers get ever thinner and calibration required of optical methods causes problems, or finding defects caused by rapid thermal annealing.
Petra Feichtinger, US applications manager, says Bede will show some comparative data developed with a customer later this year, and is looking for more beta sites to develop more failure rate data. Bede now has one tool in house and a couple out in companies. The goal over the next few months is to get throughput to 50 wafers/hr, with several measurement points per wafer.
OnWafer Technologies, Dublin, CA, is reporting data from its new PlasmaRx software, which reportedly can quickly analyze the root cause of plasma etch-chamber variation by teasing out gas flow, pressure, RF power, chuck temperature, and helium cooling problems, all from the temperature map wirelessly transmitted from the chamber by one of the company’s sensor wafers. The map is compared to a library of known variations. “What you can tell about your process and chamber from temperature data is more powerful than people imagine,” said Paul MacDonald, director of plasma and mask products.
Also tackling the problem of monitoring processes in harsh conditions is the three-person startup Verionix, North Andover, MA, which is introducing a brick-sized gas analyzer that can monitor gas composition directly at typical process pressures and in typical corrosive gas streams, without the filaments or differential pumps that present problems with more conventional gas analyzers in these aggressive chamber conditions. The product is currently in beta release, with several installations in the field at key accounts. Founder Chris Doughty notes the analyzer has shown the ability to directly monitor ALD process chemistry in real time at pulse durations down to 100msec.
Chapman Instruments, Rochester, NY, says it can measure ultrathin wafers after back grind right through the tape, with resolution down to 0.1µm, by using an optical system instead of the usual impedance method. “Capacitance systems have to make assumptions about the tape,” says Chapman CEO Tom Bristow. “And at under 100µm, it starts to matter.”
Chapman uses a laser, but doesn’t look at surface height. It splits the laser to shine a 1µm beam on each side of the wafer, and measures the angle of deviation of the return beams reflected back to an ultrasensitive detector to figure wafer thickness. The small beam can also fit between the bumps on a bumped wafer, so it can measure the actual wafer thickness and not have to calculate the average over the wafer. The company says it’s ready for its first outside beta site. - P.D.
Eliminating Ta barrier removal
ACM Research believes that its latest stress-free polishing process, Ultra SFP, has made a paradigm shift possible with respect to preserving an effective k (keff) value for the interconnect film stack. The process flow eliminates the need to remove the tantalum (Ta) barrier, which is expected to become more significant as the industry appears to be moving toward using Ta as a barrier at the 65nm and 45nm nodes (thinner Ta layers can be used compared to TaN). David Wang, president and CEO, ACM Research, says a volume of electromigration data is available based on the interface between Ta and Cu and that researchers have reported no Cu diffusion through the Ta barrier into silicon until 650°C.
“When the barrier is pure Ta, the electrochemical polishing process removes the final copper overburden and then anodizes the Ta barrier film to tantalum oxide (TaO), a dielectric that does not have to be removed and is compatible with the interconnect structure,” Wang says. By not removing the barrier layer, there is a continuous cap over the delicate low-k or ultralow-k film.
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In June, ACM Research presented consultant data that calculated the coupling capacitance between adjacent lines and the total capacitance of the entire stack (see table). “TaO does affect the capacitance,” explains Wang. “However, the reason the capacitance only increases 5-10% is because the TaO layer is very thin. The key is to keep the thickness <10nm.”
 ACM Research’s auger depth profile post-SFP for a) a 25Å Ta barrier and b) a 50Å Ta barrier. |
The company believes the new process flow is applicable to the 90nm, 65nm, 45nm, and 32nm nodes. “For the 90nm node, the TaO thickness should be 10nm, and for the 45nm node, it should be 5nm,” suggests Wang (see figure). - D.V.