A Roadmap perspective: Revisiting DFM
09/01/2005
Solid State Technology asked experts to comment on the implications of Roadmap requirements on DFM.
Gate CD control: Beyond ‘no known solutions’
John Sturtevant, Design-to-Silicon Div., Mentor Graphics, San Jose, California
 John Sturtevant |
What battered process engineers have known for several technology generations was underscored in the 2004 update to the International Technology Roadmap for Semiconductors (ITRS): There are “no known solutions” to achieve the production gate critical dimension (CD) control “requirements.” In fact, these global targets have been subsequently embellished by process engineering management’s drive to reach even more aggressive targets for fear of achieving only “industry-average” results.
Moreover, a thorough accounting of production data across all domains (tool-to-tool, lot-to-lot, wafer-to-wafer, across-wafer, across-field, and across-chip) reveals that overall gate CD control has never met the strictest of the SIA/ITRS requirements. The 1997 Roadmap featured a gate CD control target of ±20nm 3σ, applicable to all IC technologies. But the world’s best fabs were at that time likely nearing this target only for a 0.25μm chip mean CD variability, while the principally systematic across-chip linewidth variation (ACLV) was at least this magnitude and was being recognized as the dominant mode in overall gate variability. At the same time, optical proximity correction solutions were emerging, along with an understanding of the mask error-enhancement factor and the need for tighter mask CD control.
By 1999, logic had overtaken memory as the main vehicle for process technology development, and a distinction was made between the unique considerations of memory, ASIC, and microprocessor (MPU) chips, which was largely in recognition of the attractive market price/performance benefits accruing to best achievable CD control for MPUs. The MPU target for 0.18µm technology that year was ±14nm 3σ, but the world’s best post-etch gate CD distribution for lot-to-lot mean was likely only slightly better, and accounting for best achievable control across a 200mm wafer meant that the total chip mean variability was far off the target. Inclusion of the ACLV rendered the total gate CD control >2× larger than the requirement.
Lower and lower k1 imaging drives a greater need for reducing process input variability, and remarkable progress has been made across the full spectrum of owners. In fact, the steady industry progress in reducing component manifestations of CD variability has been astonishing. Advanced process control (APC) methodologies, for instance, have greatly reduced lot-to-lot variation. Projection lenses are today designed at numerical aperture values thought impossible 10 years ago, and are manufactured with incredibly low levels of aberrations. Highly accurate models are now available to work with efficient algorithms to correct full chip layouts, nearly eliminating the systematic proximity effect inherent to low k1 patterning. So there is cause for great optimism in regard to continuous improvement; after all, optical lithography itself was supposed to die long ago.
However, it is time for a realistic assessment of the Roadmap requirements vs. what the industry has been able to achieve. We need either to collectively admit that the CD control “requirements” are merely aggressive targets (and that failure to achieve such will not result in the bankruptcy of a microprocessor manufacturing company) or to accelerate the move toward disruptive device, circuit, and chip design-for-manufacturing (DFM) initiatives that will truly mitigate the impact of variables in a fab.
The latter would allow for a relaxation of the current gate CD control trajectory to close the huge gap between the proposed requirement and actual performance levels. The 2005 requirement of 2.9nm 3σ total CD control for microprocessors is clearly not going to be achieved: The CD variability of a single gate alone, due to line-edge roughness (LER), is approaching 2× that value.
The fact that LER appears to be fundamentally attendant to low k1 patterning may hasten the adoption of vertical transistor architectures, where “CD” corresponds to a film thickness, which may be more uniformly maintained across the channel. Other proposed architectures or optimum utilization of dual threshold-voltage transistors may offer relief as well.
What about “litho-friendly design” or variation-robust design methodologies? With conventional CMOS transistor design, gate leakage limits parametric yield on the short-channel side, but are minimum drawn gates being too widely employed in high-performance designs? Could process-aware selective gate upsizing be done on nontiming-critical paths? Are radically restricted design rules required to limit spatial variability in the target layout domain to much lower levels? Designers have begun to use statistical timing analysis to ensure appropriate guardbanding for timing closure, but they could better leverage knowledge of the systematic nature of intrachip CD variability.
Any new DFM pathways for accounting for manufacturing variability of gate CD must start with a thorough quantitative evaluation of actual performance and an understanding of the consequences of such capability. Despite tremendous advances in recent years, the process engineer who celebrates a 10% improvement in some targeted metric as a “breakthrough” knows perhaps there is a 200%-300% shortfall of actual total gate CD control vs. the ITRS target.
For more information, contact John Sturtevant, PhD, RET tech support manager at Mentor Graphics, 8005 SW Boeckman Rd., Wilsonville, OR 97070; e-mail [email protected].
Next ASIC fabric: Standard metal
Zvi Or-Bach, eASIC, San Jose, California
 Zvi Or-Bach |
Silicon fabrication has been going through major changes and discontinuities as process technology geometry scales down. Until the mid-1990s, the lithography wavelength was smaller than the features drawn by it. Since then, however, the lithography wavelength has become longer than the feature size. And while this discontinuity was predictable for many years, all efforts to come up with a viable alternative to optical lithography have failed. Instead, the industry started to use the wave properties of light, together with the integration and threshold properties of photoresist, to achieve sharp subwavelength images (i.e., reticle enhancement techniques (RET): optical proximity correction and phase-shift masks).
Amid these lithographic challenges, the real issue is that RETs do not really solve the problem. With dense layout patterns, the industry simply cannot get the perfect desired pattern on silicon because the various required patterns interfere with each other; as scaling down continues, this proximity effect extends even further. The impact is clear: Yield, once controlled by spot defects and die area, is now controlled by alignment and printability. These feature-limited yield issues are driving the electronic design automation industry to invest in exploring design-for-manufacturability or design-for-yield solutions.
One solution for feature-limited yield loss is to use a fabric with repetitive patterns, such as that employed in static random-access memory (SRAM) bit cells. SRAM occupies a significant amount of die area in most designs; therefore, foundries are expending enormous effort to optimize the SRAM bit cell. Using aggressive design rules, the area of the typical foundry-provided bit cell is half of what it would have been, had standard logic design rules been followed. The fact that SRAM bit cells are used in large repetitive arrays enables foundries to overcome the proximity effect by trial and error. They use aggressive bit cells in large arrays and protect them from the nonrepeating surrounding patterns with dummy cells at the array border.
Using repetitive patterns in critical poly and metal layers is the foundation of a new proposed solution to lithographic yield loss. This is the standard metal approach: an ASIC array where all metal layers are standardized and prebuilt, and customization is done through lookup table (LUT)/bit-stream for the logic functions and through single-via mask for connectivity.
Along with feature-limited yield, the fact that interconnect delay is dominating transistor gate delay shows that a standard metal fabric is needed. While feature scaling provides great economic value and improved performance, it also increases resistance and overall interconnect delay. For years, transistor delay was dominant, but continuous scaling has resulted in a crossover to interconnect delay domination, which affects advanced logic design. The industry has addressed this discontinuity with huge investments in process change from aluminum to copper, and continuous efforts to move to low-k dielectric isolation layers.
Despite efforts to alleviate interconnect delay, the domination of interconnects is threatening the timing, power, and cost of next-generation chips. The immediate implication is of diminishing returns being obtained from scaling, as the performance is no longer doubled with the next process geometry. To sustain Moore’s Law, innovation is needed.
The anticipated innovation should change the basic logic building block from fine-grain to coarse-grain for an optimized cost-performance solution. The natural choice is the LUT, which has proven to be the most successful logic primitive in field-programmable gate arrays (FPGA). Constructing logic functions using coarse-grain primitives is becoming far more efficient than using multiple fine-grain gates connected by routing wires, which are associated with high delay. Thus, bit-stream defined logic, as featured in standard metal ASIC, will become the preferred logic fabric.
The main advantage of coarse-grain logic fabric is the routing, which eventually enhances yield. A logic fabric constructed from repetitive coarse logic cells efficiently uses segmented routing, similar to FPGAs. eASIC for example, has hand-crafted a coarse logic cell, repeatedly used in the logic fabric. The interconnect is constructed with fixed segments, and in accordance with the cell length, stitched with jumpers and vias. eASIC’s standard metal fabric employs the four upper metal layers (4-7) for routing and uses the lower standard metals (1-3) for the logic. This connectivity fabric is customizable by a single via layer, complementing the LUT-programmed logic fabric, which, taken together, compose the standard metal fabric.
The transition from the popular standard cell to standard metal fabric will require a learning curve and an adoption stage. Yet, since the need for such a transition has become crucial, the pendulum will eventually swing to standard metal. As customer needs and industry trends drive the changes, history will repeat itself. About 20 years ago, standard cell started to displace full custom as the preferred logic design methodology, and now standard cell is destined to be replaced.
For more information, contact Zvi Or-Bach, founder and CEO of eASIC, 2242 Camden Ave., Suite #203, San Jose, CA 95124; ph 408/879-9400, fax 408/879-9430, e-mail [email protected].