System-on-Chip: Process integration solutions for 0.18μm embedded microFlash
09/01/2005
Processing challenges have made it difficult to put flash memory on the same chip with CMOS logic. Using microFlash technology with some modified process steps enabled this integration to be implemented on 0.18µm CMOS system-on-chip designs in small cell sizes at high yields.
A key driver for developing advanced technology generations of systems-on-chip (SoC) is enabling a higher level of embedded flash integration. The embedded process should maintain CMOS capabilities such as performance, process design kit, and intellectual property, while adding the on-chip flash features required for most of the chip sets. In addition, the total cost of an SoC application must be kept comparable to the main alternative - a two-chip set.
 Figure 1. Schematic description of microFlash cell with local trapping in the nitride layer of ONO at both sides of the channel. |
Although microFlash technology (Fig. 1) [1] has considerable advantages over other flash memory technologies in terms of ease of integration, shallow topography, and number of masks, integrating a flash module on 0.18μm CMOS introduces many challenges, which include:
- CoSi use for word line (WL),
- avoidance of Si mechanical stress due to the additional high-voltage gate oxide (HV GOX) [2],
- protection scheme to decouple the memory array from the CMOS part,
- suppression of ONO charging for narrow WL, and
- thermal budget control.
This article addresses a number of process integration solutions developed to overcome these challenges.
Recent advances in process technology have succeeded in keeping CMOS device properties unchanged, as well as meeting state-of-the-art targets of embedded memory cell size (0.31μm2/2bit), access time <33nsec, and endurance of 100,000 cycles. The developed process supports a variety of flash modules with densities ranging from 0.5-32Mbit and diverse specifications for access time, BUS width, and other internal options.
Embedded process integration
The embedded memory process involves the assimilation of memory cells and HV devices into a core CMOS process flow. Process integration efforts mainly focused on two process modules: memory cell formation and gate module (Fig. 2).
 Figure 2. 0.18µm embedded flash process flow. |
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Process development
Memory module integration. The memory storage media are deep traps introduced in the nitride-top oxide interface of the ONO stack. These deep traps and the top oxide layer are created by oxidation of the nitride at 1000°C. The high-temperature process implies that the ONO layer should be integrated before the CMOS device forms. The ONO formation step was introduced early in the process flow in order to maintain the CMOS thermal budget. The ONO stack formation is then followed by bitline etch (BLE) and BL implant (BLI), and then a BL oxide (BLO) step is introduced to create isolation between WL and the active area.
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Scaling. Adjusting the memory cell to the 0.18μm process (see table) was done by reducing the memory transistor width (Wd), memory transistor length (Ld), bitline width, and BLO. Wd was adjusted according to 0.18μm design rule capability. BLO and Ld both influence effective channel length (Leff) and were adjusted together to achieve minimum Leff. BLO processing is done after BLI and drives the BLI. As a result, Leff is reduced (Fig. 3). Optimal BLO thickness was found to be 500Å, where thicker BLO resulted in lower Leff and problems of 2bit separation and too thin BLO caused WL isolation problems. Leff was measured using special test structures [3] emulating the memory array.
 Figure 3. Leff dependence on BLO. |
To prevent excess BL oxidation during the subsequent middle-voltage (MV) and HV oxidation steps, a nitride capping layer (NCL) was introduced over the memory layer. The NCL also serves to protect the ONO layer from the thinning of its top oxide layer during CMOS clean steps and any contamination that may occur during the subsequent CMOS steps. Such contamination control is critical for achieving high product reliability. The NCL is removed prior to low-voltage GOX.
CMOS compatibility. To minimize additional process steps, the well implants were done through the ONO without additional “screen oxide,” thus preventing implant damage. The CMOS device reliability properties showed some improvement. Figure 4 shows time-dependent diode breakdown (TDDB) using different implant screen layers.
Gate module. The gate module introduced many integration challenges, mainly avoiding additional Si stress, incorporating Co-salicide WL without creating shorts between BL, and avoiding ONO charging phenomenon associated with Wd scaling. To overcome these challenges, the following solutions were developed.
Si stress. Mechanical stress in Si can influence CMOS device properties, resulting in low yield of dense SRAM [2]. During the MV/HV oxidation step, mechanical stresses are developed due to oxidation inside the STI - especially in intensive dense STI geometries. To avoid excess mechanical stress in Si during the added HV gate oxidation, we optimized the MV and HV gate oxidation processes. MV/HV GOX temperature was elevated from 750°C to 850°C. The temperature change required tuning of the CMOS device implant condition. The memory transistor proved to have low sensitivity to the thermal budget change.
 Figure 5. Word lines after the gap-filling step. The top of the WL is exposed for salicidation process. |
Co-salicide. Access time specifications required low resistance of the WL. This specification was accomplished by both WL CoSi and WL metal strapping. As WL is running over ONO and BLO, it was necessary to prevent salicidation between WL. To solve this problem, a “gap-filling” step using dielectric deposition and an etch-back process were introduced (Fig. 5). The gap-filling steps were done prior to CoSi, ensuring that inside the memory array only the top part of the WL would be salicided.
 Figure 6. Mechanism of UV charging. |
ONO charging. Reducing the Wd introduced a greater sensitivity to UV/electrical charging. UV light is emitted during the plasma processes, mainly at the metal etch step. Excited electrons from Si and poly cross the oxide barrier and are trapped in the nitride near the WL edge (Fig. 6). The undesired programming [4] cannot be easily erased. As WL become narrower, the charging becomes more dominant and Vt shifts on the order of 1-2V (Fig. 7) are observed.
 Figure 7. Vt as a function of Wd, with and without a UV protective layer. |
Adding a polysilicon layer that covers the entire memory array blocked the UV light and suppressed UV charging. As a result, the Vt roll-off as a function of Wd was significantly reduced.
Flash cell reliability
Reliability and array effects were studied using a 2Mbit product. Optimization of memory cell drain engineering and program erase algorithms were carried out simultaneously with the integration efforts. The results were excellent.
 Figure 8. Tower’s 8Mbit embedded flash module. |
A high-temperature Vt shift is temperature-activated (Fig. 8) and consists of a bound “fast” region with low activation energy and a “slow” region corresponding to the activation energy of traps in the nitride. The “slow” high-temperature Vt decrease is registered after the phase of “fast” Vt loss. Results of activation energy measurements in the “slow” region for 2Mbit arrays are presented in Figure 9. One can see that Φ ≈ 1.95eV in comparison with 1.7-1.8eV in the 0.5μm microFlash technology.
 Figure 9. Lifetime activation energy of 2Mbyte array in retention brakes (slow region of Vt decrease). |
The obtained value of Φ ≈ 1.95 eV is significantly higher than 1.7~1.8 eV achieved in previous 0.5μm technology. This ensures excellent retention performance for applications requiring high-temperature operation. We attribute these improvements to optimal ONO fabrication process and less influence of backend processes.
Conclusion
A state-of-the-art 0.18μm embedded flash process has been developed that is distinguished by small cell size, low cost, high performance, and high yields. The core CMOS characteristics remained unchanged. Experience with microFlash technology kept development time short and minimized costs.
References
- B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, et al., “NROM: A Novel Localized Trapping 2-bit Nonvolatile Memory Cell,” IEEE Electron Device Lett., Vol. 21, pp. 543-545, Aug. 2000.
- R.A. Bianchi, G. Bouche, O. Roux-dit-Buisson, “Accurate Modeling of Trench Isolation Induced Mechanical Stress Effects on MOSFET Electrical Performance,” STMicroelectronics, IEEE 2002.
- Y. Roizin, A. Yankelevich, Y. Netzer, “Novel Techniques for Data Retention and on Leff Measurements in Two-bit microFLASH Memory Cells,” AIP Conf. Proc., No. 550, pp. 181-185, 2001.
- M. Lisianski, Y. Roizin, M. Gutman, S. Keysar, A. Ben Guigui, et al., “ONO Charging at Different Stages of the microFlash Process Flow,” Tower Semiconductor, ICIDT, p. 231, May 2004.
Menachem (Nachi) Vofsi is director of marketing applications at Tower Semiconductor, Migdal Haemek, Israel; e-mail [email protected].
Ephraim Aloni is senior specialist and leader of the NVM integration team and has worked at Tower Semiconductor for more than 12 years.
Pavel Zisman is currently with Intel Semiconductors, but previously was with Tower Semiconductor as NVM device specialist of the 0.18μm embedded NVM project.