Issue



A novel technique for sealing porous dielectrics


08/01/2005







As the industry moves toward the 45nm node and beyond, pore sealing is critical to enable the integration of porous low-k dielectric materials. The addition of porosity to the low-k film, together with scaling requirements for finer dimensions, raises significant challenges.

During damascene patterning, the porous low-k material is exposed to a series of chemical processes including plasma etching with fluorocarbon chemistries, ashing with oxidizing and reducing chemistries, chemical vapor deposition of precursors, and post-ash residue wet cleaning.

Metal or precursor penetration into the dielectric during the ALD or CVD processes results in increased leakage and increased capacitance, while degrading the reliability of the device structures. In addition, etch and ash processes that are needed to pattern the dual-damascene structures may cause significant physical damage to the dielectric that affects copper and precursor penetration. The damage to the dielectric may also manifest itself in the form of carbon depletion, surface roughness, increased moisture absorption, and an increase in keff of the integrated structure [1].

Methodology and results

At Sematech, various pore-sealing materials and processes are being evaluated. Some of the criteria used to screen these material systems include the ability to:

  • block precursor and copper penetration into the pores;
  • scale beyond the 45nm node;
  • cause minimal increase in the keff after pore sealing; and
  • have good adhesion to the subsequent barrier layer.

The analytical techniques used to test the quality of the pore sealing vary from SIMS analysis, TEM/EELS, solvent infiltration, leakage measurements, and cyclic voltammetry [2].

Pore-sealing processes screened at Sematech include spin-on and CVD liners, surface treatments, and alternate processing schemes that incorporate inherent pore sealing. While these processing schemes have shown some valuable features, they have not led to a complete solution that addresses the four criteria listed.

Subsequently, a novel pore-sealing technique has been developed at Sematech. The method uses a conformal CVD material deposition that partially penetrates the vertical walls of the etched dielectric to seal the pores but does not leave an “overburden” of pore sealant on the sidewalls. In this process, the size of the pore-sealant material’s molecules was tuned to complement the pore size of the low-k material, enabling the sealant to penetrate the low-k surface. In addition, the process sequence was changed to eliminate the excess pore sealant.


Figure 1. a) A cross-section TEM of a sample pore-sealed by Sematech’s new process; b) EELS analysis showing reduced carbon depletion (5nm) at the low-k Ta interface in the pore-sealed sample; and c) EELS analysis showing a relatively high degree of carbon depletion in an unsealed sample (15nm).
Click here to enlarge image

The new approach provided both pore sealing and protection from dielectric damage, as shown by the data in Figs. 1 and 2. Because a CVD process deposits the pore sealant with a very high degree of conformality, continuous sealing was observed at small and large features. The effectiveness of pore sealing in patterned wafers can be studied using TEM/EELS analysis for Cu penetration and dielectric damage.

Trench samples after metallization and passivation were annealed to 400°C for 60 min and then examined by TEM/EELS analysis for Cu penetration. As shown in the TEM in Fig. 1a, no Cu penetration into the low-k was observed. The extent of dielectric damage can be determined by estimating carbon depletion using TEM/EELS analysis (see Figs. 1b and 1c). It is clear that the process (see Fig. 1b) leads to significantly lower carbon depletion.


Figure 2. Cyclic voltammetry data showing exposed Cu in an unsealed sample, compared with the absence of reaction current in trenches sealed with a new process.
Click here to enlarge image

As a followup to the TEM analysis, a more sensitive technique known as cyclic voltammetry was used to study the effectiveness of pore sealing. The cyclic voltammetry result in Fig. 2 shows no reaction peaks associated with Cu redox reaction, indicating that there is no exposed Cu along the sidewall of the trench. The new process was also investigated for its effectiveness in blocking ALD tantalum from the porous low-k dielectric using a SIMS analysis. SIMS data showed that the pore sealant successfully blocked ALD Ta.

While dual-damascene builds have not been discussed here, the new process can be readily extended to a via-first-trench-last process by using two consecutive process sequences.

Conclusion

A pore-sealing method that will have minimal impact on keff not only seals the porous low-k to avoid barrier and Cu penetration, but also addresses the issue of low-k damage.

Currently, the major barriers to large-scale implementation of porous low-k materials are dielectric damage and the need for pore sealing when used in conjunction with ALD barriers. In the event that the industry finds it impractical to commercialize such a process, low-k material manufacturers will have to engineer damage-resistant low-k materials that would require no pore sealing.

References

  1. S. Satyanarayana, R. McGowan, B. White, S. Hosali, “Damage Mechanisms in Porous Low-k Integration,” Semiconductor International, June 2005.
  2. C.-U. Kim, J.-Y. Park, N.L. Michael, Y.-J. Park, S.H. Kang, et al., “Detection of Barrier Failure in Interconnects with Ultralow-k Materials: ICV Voltammogram,” Advanced Metallization Conf., Oct. 2004.

Sri Satyanarayana received her PhD from the U. of Texas at Arlington. She is a member of the technical staff at Sematech, 2706 Montopolis Dr., Austin, TX 78741; e-mail [email protected].

Eric Busch, Sematech assignee, received his his MS from the U. of New Haven, CT. He is module manager at Advanced Micro Devices, One AMD Place, Sunnyvale, CA 94088; e-mail [email protected].