Coupling substrate and architecture with thin-layer transfer technology
08/01/2005
Silicon-on-insulator (SOI) is the first example of an engineered substrate with an active top Si layer decoupled from the support wafer by the buried oxide (BOX), thereby addressing mainstream MOSFET performance requirements. The ability of SOI to enhance the performance of partially and fully depleted devices, reduce device leakage and power consumption, and be suitable for low-voltage device architectures has been thoroughly discussed in the literature.
This article will review the latest developments in substrate engineering driven by IC industry requirements and show examples of composite substrates of interest from other fields such as optoelectronics, RF, and high-power management. Soitec’s Smart Cut layer transfer technology has made it possible to build transistor performance-enhancing features into the substrate and couple device architecture and composite substrate.
Mobility-enhancing substrates
45° notch rotation SOI. For standard (100) Si substrates, the notch or flat is aligned along the <110> direction and the current flows along the <110> direction. However, as reported in 2002 by T. Matsumoto and coworkers from Renesas, by rotating the transferred (100) layer 45°, transistors become aligned with the <100> direction. Although no effect is seen on the nMOSFETs, the mobility is enhanced by 16% for those p-channel devices with wide and long channels. For narrow p-devices, a mobility enhancement of 67% has been observed because hole mobility is less affected by CMOS process-induced stress along the <100> direction than along the <110> direction.
Hybrid orientation SOI. A further enhancement of p-channel devices can be achieved by transferring a (110) Si layer onto a standard (100) substrate. In 2003, M. Yang and coworkers from IBM revealed that in this case, a mobility enhancement of 70% is observed for long p-channel devices. In contrast to the 45° notch rotation SOI approach, however, the nMOSFET on the (110) plane suffers a 35% mobility decrease. To avoid this issue, a composite SOI substrate of a (100) layer on a (110) base is proposed. The nMOSFET is made on the (100) Si layer while the pMOSFET is made on the (110) surface.
Strained SOI. More recently, it has been shown that strained silicon-on-insulator (sSOI) and strained silicon on relaxed silicon-germanium-on-insulator (SGOI) significantly improve the mobility and current drive of n- and p-channel devices depending on the Ge content of the SiGe template used to create the strain, as initially shown by Tagaki and coworkers from MIRAI. The effect of the strain on a (110) SiGe surface also leads to a significant hole-mobility enhancement, and, depending on the substrate fabrication, there can be mobility enhancements for n- and p-channels as well.
For a strained-Si film grown on a fully relaxed SiGe (20% Ge) template, a biaxial stress level of 1.3-1.5GPa is achieved. This leads to a mobility enhancement of 80% for nMOSFETs, resulting in a current-drive increase of 40%. If the concentration of Ge is increased up to 40%, the same level of mobility enhancement is also achieved for p-channel devices.
The fabrication processes of sSOI and SGOI are similar and have many steps in common with the SOI process flow. Both sSOI and SGOI substrates are robust; annealing experiments show no strain relaxation up to 1100°C with proper surface passivation. Sadaka and coworkers from Freescale Semiconductor reported in 2004 results for 45nm SGOI n-channel devices that showed mobility enhancement of 67% and current-drive increase of 18%, indicating that no significant strain relaxation occurs down to 45nm. Transistor and gate oxide reliability studies gave comparable results to SOI control samples, pointing out no detrimental effects due to the underlying SiGe film.
 Figure 1. TEM micrographs of sSOI fabrication after a) bilayer transfer and b) selective removal of SiGe. |
Strained SOI has captured the attention of the IC industry because it offers the benefits of strained Si without the constraints related to processing a Ge-containing substrate. Figure 1 shows the making of sSOI. Recent progress on defect reduction in donor wafers as well as Smart Cut processing improvements have enabled production of sSOI substrates with strained film thicknesses from 10nm up to 40nm. The resulting sSOI for the different thicknesses is fully strained. Macro-Raman measurements (10×10cm) for a 40nm-thick strained-Si layer on insulator show an average strain level over the wafer of 1.55GPa with a 1σ uniformity of ±0.065GPa. Micro-Raman measurements before and after an 1100°C anneal are shown in Fig. 2.
 Figure 2. UV micro-Raman (364nm) results for a 50×50µm scan: a) finished sSOI and b) after oxidation and an 1100°C anneal. Average strain is 1.20 and 1.28GPa, respectively. |
Currently, sSOI for partially depleted device architectures with strained-Si film thicknesses of up to 70nm is under development. Recent results by Thean and coworkers of Freescale (presented at the VLSI Symposium of Technology in June) for partially depleted device and SRAM results highlight the benefits of sSOI substrates with supercritical thickness to maximize nMOSFET performance. This work in particular shows that the strain is maintained even for transistors as small as 40nm.
Germanium-on-insulator. GeOI is the newest development among the mobility-enhancing substrates and is of interest for high-performance CMOS ICs, as well as for photodetectors and solar cells. The Ge donor wafer can be an epitaxially grown Ge layer on a Si substrate or a Ge bulk wafer. The epitaxial approach to the Ge donor is easily scalable to 300mm but suffers from a large number of crystal defects. Processing a Ge surface is a difficult task because the typical cleans developed for Si tend to etch and roughen the Ge surface.
Improved thermal-conductivity substrates. Silicon oxide is a poor thermal conductor. An improvement of the buried dielectric’s thermal conductivity could reduce the transistor self-heating effect by >50°C, thus improving the n- and p-channel carrier mobility by >50%.
The simulation study by Cristoloveanu’s group presented at the International SOI Conference in 2004 shows that a reduction in BOX (SiO2) thickness from 200nm to 20nm increases the SOI thermal conductance by a factor of ~3. If the buried oxide were replaced by diamond, an improvement of at least 4× should be expected.
RF and optoelectronic applications
Beyond microelectronics, thin-layer transfer technology makes it possible to design new types of substrates for a host of applications. One example is double SOI for photonics applications where the photodetector is built into the first SOI layer, with the IC built on the top Si layer. Another example is silicon-on-quartz (SOQ), which is useful for displays or RF applications because of its insulating substrate. A more evolutionary approach to RF applications is SOI using a high-resistivity handle wafer. The technique, called high-impedance SOI, has very low crosstalk and power loss, and was extensively reviewed earlier this year by Raynaud and coworkers of STMicrolectronics at the ECS Spring Meeting.
SiC-on-insulator (SiCOI) is a rapidly growing field; the handle wafer can be polycrystalline silicon carbide or silicon. It provides a suitable template for growing high-quality gallium nitride to enable production of high-quality LEDs, as shown by Letertre and coworkers from Soitec.
Conclusion
The industrial flexibility of a generic layer-transfer technique called Smart Cut has been reviewed and a broad range of applications presented. The ability of the technique to scale to any wafer size allows multiple peelings of a donor substrate, and therefore has the flexibility to combine single-crystal thin films of a given material with another substrate material to integrate the required performance-enhancing properties.
Acknowledgments
The work reviewed here reflects the efforts and results of several teams. The author would like to single out the support received by the R&D and manufacturing divisions of Soitec, and the Laboratory for Film and Circuit Transfer of CEA-LETI in Grenoble. Special thanks in particular to I. Cayrefourcq, G. Celler, B. Ghyselen, F. Letertre, and M. Yoshimi from Soitec. Smart Cut is a trademark of S.O.I.TEC Silicon On Insulator Technologies.
Carlos Mazure received his doctorate in physics from the U. of Grenoble, France, as well as a doctorate in physics from the Technical U. of Munich, Germany. He is CTO at Soitec, Parc Technologique des Fontaines, Bernin, 38926 Crolles cedex, France; e-mail [email protected].