New demand and challenges for gold-bump technology
08/01/2005
Asia has been a dynamic region for the development and manufacturing of liquid-crystal display (LCD) panels. Specifically, Japan has been the industry leader in vertically integrated manufacturing of display panels, as well as one of their key components, LCD driver ICs. However, cost and supply-chain considerations have resulted in a consistent migration of flat-panel display (FPD) manufacturing from Japan’s vertically integrated device manufacturers to merchant foundries in Taiwan, Korea, and China. This cost-driven transition has resulted in a need for additional packaging, assembly, and test capacity in various regions of Asia, particularly in Taiwan and China.
This article examines technology trends and manufacturing challenges in LCD driver packaging throughout Asia. Production criteria that foundries must consider to achieve operational success also are discussed.
Market and technology
Demand for larger, higher-resolution thin-film transistor (TFT) displays, particularly for use in graphic-intensive applications, is increasing at a brisk pace. TFT-LCD is the dominant display technology for most electronic systems associated with high information content. Growth in the LCD market segment also has fueled an increased demand for row and column driver ICs.
According to market research firm Gartner Dataquest, the FPD market is expected to increase at a 10% compound annual growth rate (CAGR) from 2004-2008. Significant growth in data-processing electronics, such as handheld computers, notebook computers, and flat-panel monitors, is contributing to this growing demand.
TFT-LCD driver ICs are responsible for sending and converting the electrical signals on the LCD panel to form visible images. The driver ICs are attached on the display panel along the outer vertical and horizontal perimeter. Two types of ICs are used - source drive ICs (also called data drive ICs), mounted in the x direction, and gate drive ICs (also called scan drive ICs), mounted in the y direction. The quantity of these chips required depends on the display panel size and resolution. Typically, a 12-in. SVGA (800×600) TFT-LCD panel requires ~12 driver ICs.
Migration to Asia
While the gross margin for most analog chip production is still fairly high, increased consumerization of display devices and consequent downward pricing pressure has resulted in significant price erosion for driver ICs. To meet the demand requirements, device manufacturers are outsourcing both driver IC fabrication and final assembly and test operations to various wafer foundries in Taiwan and China. This situation has hastened the migration from Japan and created a significant business opportunity for Asia’s semiconductor assembly and test sector, particularly in the gold-bump market. Figure 1 illustrates the regional capacity distribution for the gold-bump market in Asia.
Outside of Japan, the most active regions in Asia for the supply of driver ICs are Taiwan and China. The foundry business model established Taiwan as a one-stop shopping center for key FPD components. A number of suppliers in Taiwan positioned themselves as the “turnkey” solution provider. Major suppliers in driver IC packaging and testing operations include ChipBond, ChipMos, IST, Megic, Aptos, and Fupo. With the planned merger between ChipBond and Aptos, ChipBond will become the world’s largest driver-IC backend turnkey supplier. Once the merger is complete, ChipBond reportedly will increase its gold-bumping capacity (6- and 8-in. wafer size equivalent) to 135,000 wafers/month.
Challenges in gold-bumping lithography
The rapid migration of the driver IC business from Japan is inducing Taiwan’s manufacturers to adopt similar technology and production methods. For gold bumping, photolithography is one of the most critical manufacturing processes. The shape of the gold bumps depends on the effectiveness of the photolithography step. The Japanese bump plating process was mainly developed on thick (>15μm) positive-type photoresist to achieve bump height requirements. While the lithography requirements for gold-bump manufacturing are subject to the same production and yield demands as frontend semiconductor fabrication, the considerations for backend lithography are significantly different. Some of the unique requirements for these advanced packaging lithography applications are summarized in the following sections.
Thick-resist lithography. Unlike the wafer-fabrication photolithography process, the gold-bumping process requires image reproduction into thick photosensitive films. This places greater emphasis on consistent critical dimension (CD) control, which is necessary for uniformity in bump height across the wafer. The thick photoresists also require a large exposure dosage for high aspect-ratio lithography. For these reasons, Japanese manufacturers have been utilizing projection lithography tools to achieve the above-mentioned requirements for the gold-bump process (Fig. 2). In addition to imaging quality, advanced pattern alignment capability is also critical to address gold-bump manufacturing requirements. Utilization of projection lithography has become one of the key technical requirements for outsourcing business to Taiwan.
 Figure 2. SEMs of 15μm space/10μm lines created with projection lithography. (Images courtesy of JSR Micro) |
Wafer-edge processing requirements. After the photoresist is patterned, the wafer is processed for gold deposition by electroplating, which requires the outer edge of the wafer to become the electron contact in the plating bath. It is important for a photolithography system to either exclude or expose the outer edge of the wafer to ensure electrical contact during the plating process step.
Volume production considerations. To ensure successful volume production in a cost-competitive environment, both device manufacturers and wafer foundries must pay considerable attention to equipment productivity, flexibility, and process yields.
The ability to process various wafer thicknesses and sizes from different sources is a key requirement. Furthermore, a wafer could be severely warped by the time it reaches the photolithography process sequence. Such variability of wafer conditions will have a direct effect on the wafer yield. Because wafer bumping is one of the final manufacturing process steps, yield loss during the lithography step is unacceptable and will directly affect the bottom line. In addition, contact aligners could introduce a combination of reworkable and nonreworkable yield defects due to wafer-to-photomask contact, increasing overall production costs. Therefore, Taiwanese manufacturers have adopted 1× projection exposure technology for enhanced wafer process flexibility and yield performance improvements, resulting in lower production costs [1].
Conclusion
The outsourcing of LCD driver-IC bumping and packaging by captive driver IC suppliers in Japan has resulted in the subsequent migration of gold-bump manufacturing from Japan to the rest of Asia, where Taiwan has been the most active in ramping driver-IC gold bumping, assembly, and test capacity.
In recent years, the backend driver-IC supply chain has migrated to China due to lower manufacturing costs, partly a result of China’s role as a volume manufacturing site for flat-panel monitors. The migration has been fueled by the need for backend driver-IC suppliers to be closely aligned with the flat-panel monitor electronic manufacturing services.
Reference
- M. Ranjan, et al., “Productivity Enhancements in Advanced Packaging Lithography,” Advanced Packaging, July 2003.
Nelson Chen received his bachelors in mechanical engineering from McGill U. in Montreal, Canada. He is Asia Pacific region product marketing manager for Ultratech Inc., 3050 Zanker Rd., San Jose, CA 94041; e-mail [email protected].
Gold bumping: The interconnect for TFT-LCD panels
Before the driver IC is mounted onto the LCD panel, the chips must be bumped to form the electrical interconnects. These connections are formed by electroplating the gold onto the driver IC wafer. The location of the gold deposition needs to be defined precisely on the IC contact pad. Gold plating patterns on the wafer are defined by using thick-resist photolithography technology prior to the actual plating process, and gold-bump plating is done at the wafer level.
 A typical FPD integration scheme. (Source: Gartner Dataquest) |
Once bump formation is complete, the driver ICs are packaged using either tape carrier package (TCP) or chip-on-film (COF) technology. Shifting to new frontend manufacturing processes to address the increased brightness requirement and ensure adequate resolution has resulted in increased I/O counts for driver ICs. The increase in I/O counts along with the die shrinks has resulted in finer I/O contact-pad pitch. A TCP with inner or outer lead bonding can be used for packaging the gold-bump structure with I/O pitches >45μm. The COF package, which bonds the chip directly onto a polyimide film, is used when the I/O pitch is <45μm. To further reduce the form factor of the package, chip-on-glass (COG) packaging is also widely used.