DFM issues new rules for IDMs, foundries
07/01/2005
Solid State Technology asked industry execs to comment on the proliferation of DFM solutions and their integration into the product flow.
Design-for-manufacturing: Who is buying?
The industry has always practiced design-for-manufacturing (DFM) - even back when the obstacle to tape-out was passing design-rule check (DRC), which was meant to guarantee the manufacturability of a design. Each process would come with its own rules and the method worked well up to 180nm.
With the introduction of copper at the 130nm node, simulation and design rules started to fall behind just as the industry itself started to decline financially; the result was a demand for faster turnaround times. Product teams started to work around DRC and waive some DRC violations to get designs into the fab quickly. Interestingly, this shift allowed more projects to move forward because these violations would be worked out post-mask. (It is worth mentioning, though, that it challenged yield, and made yield-improvement techniques more critical than ever before.)
But recently, with 90nm process technology, the whole scheme has collapsed. The number of design rules soared into the hundreds and violations could not be worked around anymore. Therefore, DFM became a critical step again (and a new buzzword), as a proxy for “Can we pass DRC again in a reasonable amount of time?”
Additionally, a whole set of new tricks is now positioned between design and reticle enhancement techniques (RET). This creates a very complex transformation between design and the fab, and makes communication between design and process teams extremely challenging.
This problem is compounded by the now famous “disintegration” of the industry, namely in the form of the foundry-fabless model. This created a significant physical separation between design and process teams. Design rules would now be “thrown over the fence” instead of being developed collaboratively by both sides. Concurrently, a lot of internal mask shops were spun out or sold.
The gap between fabless and IDMs widened, with IDMs managing to use 90nm technology for specific, high-volume applications, whereas well publicized examples of fabless-foundry struggles highlighted a structural problem.
The industry is faced with a manufacturability problem, and stakeholders are now spread over three separate business entities: the design group, the mask shop, and the fab. Only six semiconductor companies retain all three functions internally.
Many people have good technical ideas about how to solve the problem, but nobody to whom they can sell the solution. Even within IDMs, few people hold the title of “DFM manager,” whereas one can find plenty of “yield managers,” for instance. Therefore, initial attempts at comprehensive, “integrated” solutions failed to find buyers. No return would be generated, drying out investment in this type of DFM.
The industry has recently zeroed in on a major technical culprit - the mask - or to be more accurate, the mask development process. The latest products dubbed DFM-enabling originate from electronic design automation companies as part of the RET flow. They are aimed at improving the ability of designs to be turned into reticle sets that actually result in yield. This is certainly a promising approach, as it channels a solution to an identified buyer - the mask shop. This should allow these solutions to be funded and adopted.
The real problem is not addressed, though, as mask-centric products will struggle to evolve dynamically in lock-step with process and design tools. The need remains for a very tight link between process and design tools. Mask-centric tools are sitting in the middle and serving two different masters.
Moving forward, only those companies with knowledge on all three sides (design, mask, and process) will be able to facilitate that link - even if, as will certainly be the case, its embodiment will be delivered primarily into the RET cycle.
DFM will become a business reality with companies that have multilevel knowledge of the entire semiconductor cycle and can sell products in each function - design, mask, and process - or to each type of customer - fabless companies, mask shops, and foundries.
Mask-centric products will promote (and fund) the DFM industry initially, but as for yield-enhancement products, a new kind of buyer will have to emerge: the DFM engineer and DFM manager. The real question is where this function will reside. The answer will shape the DFM segment and the companies that will serve it.
The DFM winners will be those companies that cultivate the deepest understanding of industry needs by leveraging customer intimacy on all sides of the semiconductor product cycle. The value created by DFM will originate in design but will accompany each semiconductor project all the way through completion in the fab; only the organizations already experiencing the struggles of design teams, mask shops, and low yield will be adequately positioned to appreciate where to create value and reap its benefits.
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For more information, contact Michel Villemain, VP, marketing, CMD, at FEI Co., 1135 Arques Ave., Sunnyvale, CA 94085; ph 408/523-9968, e-mail [email protected].
DFM issues challenge the industry
With 65nm circuits in technology development and 45nm infrastructures being put into place, one question that needs to be addressed is why have more than half of 90nm designs required at least one full-reticle re-spin? The semiconductor industry is still grappling with the answers; some hope that DFM will be a primary force that enables solutions going forward.
There are literally dozens of reasons for poor yields in case studies at 90nm, in the areas of power, new materials such as low-k dielectrics, reliability, etc. Each requires improvements in the status quo for success at 90nm and below. However, the bulk of the problem has been concentrated in two main areas: 1) simple parametric variation and 2) systematic defects.
Increased device and interconnect variance occur as so-called digital logic devices are pushed to their analog limits. Random issues such as gate oxide thickness, dopant variation, line-edge roughness, and more, are contributing to on-chip variance values that are so large as to not be practical to guard-band around…they must be understood, characterized, and statistically modeled.
Systematic causes of poor yield are the result of design-process interactions and form the basis for the classic DFM problem. Root causes include “the other low k” - i.e., low k1 lithography (RET/mask/stepper/photoresist) - and their extreme interdependency with layout topologies. Features at the 90nm node are so far below the exposure wavelength that various RETs are required, and complex, severe layout-dependent design-rule process windows result. Device variations are now dependent on simple factors such as pitch and orientation, as well as more complicated issues such as edge and corner proximity. Often overlooked, but equal contributors, are etch and CMP interactions, which manifest as variation in effective device size and local and mid-range pattern densities.
The current solution is to communicate DFM issues via binary design rules. This is clearly a case of using a system well beyond the paradigm for which it was designed. As a bandage, minimum design rules are supplemented by “recommended” design rules for high yield, but no quantification is given to the designer regarding how much yield improvement might be realized. Along this path, the number of physical design rules has increased by up to a full order-of-magnitude from 180nm to 65nm. Many of these rules are contradictory. As a compounding problem, a large number of the additional rules are statistical in nature. The result is that most technology organizations are ill-prepared to gather enough data to validate their design rules, much less process that data into information that would be useful to a designer. In a classic chicken-and-egg scenario, current CAD infrastructures lack the yield modeling capabilities to make use of such information anyway. We then ask the manufacturing fabs to monitor for weaknesses using a few dozen wafer-acceptance test structures, virtually guaranteeing hiccups in the handoff from development to manufacturing.
The solution to the deep-submicron yield problem lies on both sides of the fab/design wall. Successful infrastructures will require unparalleled levels of communication between these historically separate groups. At the large IDMs, cross-functional teams are being put into place for 65nm, and nascent internal or external tools are being readied that can truly deliver on DFM - i.e., to take yield information from the fab and present it as usable yield models up front in the design flow, concurrent with traditional design models such as speed, power, etc.
The good news for the foundries is that the problems are so vast and complex that no number of seasoned engineers can provide a long-term advantage. DFM will have to be instituted with next-generation CAD tools that are well calibrated using advanced characterization wafer data. The primary risk to foundries is in not truly buying into the fundamental concept of DFM: More and better information about the components of yield loss will be directed to the designers (who are external to the foundry). IDMs do have an advantage here in that all parties wear the same badge. This coming requirement for heightened communication from fab to designer presents a potential opportunity to second-tier foundries, if they embrace the more open-access (pun intended) DFM paradigm ahead of the top-tier foundries, which have a history of wanting to closely guard this type of information.
Another advantage that true DFM might present to the foundry/fabless community is that fixed costs could be lowered. Forget expensive mask sets - depending on the chip complexity, the design and verification costs can be 10-20× higher than that. These fixed costs could price smaller fabless companies right out of new technology nodes and allow only mainstream chips in established markets to flourish, as only those products can amortize the fixed costs over a large number of units. New technology that is too expensive for the next Xilinx or Broadcom to grow into might be the largest risk of all.
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For more information, contact Greg Yeric, chief technologist, at HPL Technologies Inc., 2033 Gateway Place, #400, San Jose, CA 95110; ph 408/437-1466; e-mail [email protected].