Introduction of stress requires stress metrology methods
07/01/2005
Although stress has been used to increase carrier mobility for the past several years, its measurement and control have also proven difficult. With the increasing demands on IC manufacturers to get more mileage out of each technology node, the use of stress as a node extender will continue for the foreseeable future. Processes used to increase carrier mobility are discussed along with metrology methods and challenges.
Stress impacts transistor and interconnect electrical properties, yield, and reliability. For example, film stress plays a role in electromigration-induced metal line failure and in the delamination of metal lines [1]. More recently, interest in stress metrology has risen due to the use of process-induced stress to increase carrier mobility, which increases transistor drive current and thus transistor switching speed [2]. Strained silicon substrates are also being investigated for this purpose [3].
Stress - the force applied to a material - comes in various forms and can be compressive or tensile. It can also be uniaxial (along one crystallographic direction) or biaxial (along two perpendicular crystallographic directions). Hydrostatic stress refers to stress applied equally in all three directions. Usually, stress-induced changes in physical properties are modeled by assuming that a material responds as if it is a continuous elastic material. Uniaxial and biaxial stresses are illustrated in Fig. 1. Measuring stress and modeling its impact require knowledge of these details. In this discussion, it is important to remember that the force acting on a region of a sample - stress - is related to the change in shape of that region - strain - through the elastic equations. In an atomistic view, stress causes strain, which is the displacement from equilibrium lattice positions. In an elastic continuum view, strain is the local displacement of a continuous slab of material from its equilibrium position.
 Figure 1. Uniaxial and biaxial stresses. |
Process-based increases in carrier mobility are already used in volume manufacturing at the 90nm technology node and in the first 65nm node chips. Transistor gate lengths in logic devices are 45nm at the 90nm node. Processes induce nearly uniaxial tensile stress to increase electron mobility and uniaxial compressive stress to increase hole mobility. Intel uses thicker silicon nitride layers above the nMOS and replaces the source and drain in the pMOS with silicon germanium (SiGe) [4]. This implies that process control requires measurement of silicon nitride (Si3N4) for controlling the nMOS and Ge for controlling the pMOS mobility. Texas Instruments has found that use of recessed SiGe source and drain extensions improves pMOS drive current by 35% [5]. Fujitsu has shown that by changing process conditions, the Si3N4 layer can be used to impart both tensile and compressive stress [6]; the referenced work provides the ultimate proof of the role of process conditions in determining the stress from a Si3N4 layer. Once the process is well established, metrologists are able to control transistor drive current by measuring the thickness of the Si3N4 in different regions. IBM uses the stress induced by shallow trench isolation (STI) to stress pMOS channels [7]. The amount of stress can be altered by changing the distance between the STI and the edge of the gate electrode. Critical modeling work has shown how compressive stress along the <110> direction of silicon increases hole mobility [8, 9].
Measuring stress
Because measurement of localized stress is very difficult, process control must be done by measuring properties of available films. The challenge is that the area of interest - the transistor channel - is buried under the transistor gate. For nMOS, the silicon nitride layer is above the transistor, and the thickness of the silicon nitride can be measured in that layer and related to stress in the channel. The difficulty with this approach is correlating layer stress with that in the channel. The relationship between the stress in the measurable layer (Si3N4) and that in the channel must be model-based. Stress in the pMOS channel is even more difficult to measure locally.
Future approaches to stress-induced improvement of carrier mobility include the use of metal gates and strained silicon substrates [10]. Strained Si substrates are grown on top of SiGe layers where the lattice mismatch provides the stress. Strained Si can either be left on top of the SiGe or transferred to a wafer with a surface oxide layer producing the so-called strained-silicon-on-insulator (sSOI). It is important to note that these layers are biaxially strained, while the channel engineering provides nearly uniaxial stress along one crystallographic direction.
At the December 2004 International Electron Devices and Modeling Conference, Thompson et. al. provided an excellent discussion of the advantages of uniaxial stress [9]. The process-based approach allows one to use compressive stress for p-channel devices and tensile stress for n-channel devices, while the substrate approach presumes that both n- and p-channel devices can improve mobility using the same type of stress.
 Figure 2. Survey of stress (strain) measurement methods. (TEM images courtesy of Intel) |
Process-based stress and stressed silicon substrates pose different problems for metrology. Although the substrate films cover large areas, they are very thin. One must work harder to make traditional methods provide reliable data for very thin films. When processing provides the stress, the challenge for measurement is the fact that the film is buried, as stated previously. In Fig. 2, stress measurement methods and their applications are summarized. Below, several measurement methods are briefly described along with the challenges each will face.
Strain measurement methods
Raman spectroscopy can measure the shift in the wavelength of the silicon optical phonons caused by strain. The shift can be related to stress through the elastic equations discussed. The measurement area is typically 1µm dia. Measurement of very thin layers has driven the use of 325nm laser light. A number of universities, including Alan Campion’s group at the U. of Texas in the Advanced Materials Research Center, are investigating the combination of scanning nearfield microscopy and Raman to greatly improve spatial resolution; this is known as nano-Raman. The method is easily applied to strained Si substrates. Measurement of test areas in scribe lines is also possible, but the only way to apply this approach to stress measurement for areas covered with amorphous Si3N4 is to measure stress in the silicon underneath the film. In the future, nano-Raman systems based on nearfield optical microscopes will push the spatial resolution to <200nm.
X-ray diffraction (XRD) has been used to measure lattice constants for more than 100 years. High-resolution XRD enables the measurement of small changes in lattice constant. XRD measurement area is typically 0.3mm2. Measurement of patterned wafers requires large test areas.
Convergent beam electron diffraction (CBED) measures the strain in cross-sectional samples during transmission electron microscopy (TEM). Although areas <1nm dia. can be measured, the sample has been cross-sectioned and thinned to electron transparency, ~100nm or less. The relationship between strain in these samples and strain in an IC is not well understood. CBED can be used to measure strain in thin strained Si layers or in transistor cross-sections.
Photoreflectance spectroscopy measures the strain-induced change in the electronic band structure of silicon or germanium. The electronic transition between energy levels occurs at specific energies that change when the lattice structure is stretched or compressed. Biaxial stress splits energy levels that are degenerate in unstrained silicon or germanium. In particular, the E1 transition energy at 3.392eV is used to monitor strain and in Fig. 3, the characteristic split E1 transition of biaxially strained Si is shown. This method has been applied to unpatterned wafers.
Wafer- or die-level stress measurement methods
The average stress can be determined across a wafer by measuring the change in wafer curvature after film deposition. This method has been used for years to control interconnect film stress. Interferometry measures local wafer curvature, extending stress measurement to the die level. The new coherent gradient system (CGS) uses a referenced interferometer to measure local curvature of the wafer at a pixel spatial resolution of 300µm. Using well known algorithms, the local stress changes can be calculated from the local wafer-curvature changes when a wafer is measured before and after a process step.
Conclusion
Substrate and process-based increases in carrier mobility using a variety of methods (e.g., uniaxial tensile stress, compressive stress, and combinations of both) are already seen in volume production at the 90nm node and are also being used for 65nm node chips just beginning production development. The broad array of stress/strain technologies also requires a variety of metrology methods, including nano-Raman, CBED, and photoreflectance spectroscopy at the device level, and CGS at the wafer level.
The use of stress to increase carrier mobility will continue. Process-induced uniaxial stress can be applied through several different means, including silicon nitride cap layers. Stress measurement is most easily done on unpatterned wafers, but the measurement of stress in patterned wafers is largely under development.
Acknowledgment
CGS Measurement Technique is a trademark of Oraxion Diagnostics.
References
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Alain Diebold received his BS and PhD in chemistry, and is a post-doctoral Fellow in surface science. He is a Senior Fellow at Sematech, 2706 Montopolis Drive, Austin, TX, 78741; e-mail [email protected].