Improving yield at 65nm using Cu thickness monitoring and control
07/01/2005
The dual-damascene process used to create copper interconnect exhibits nonuniformities in both Cu deposition and removal rates that, if not closely controlled, result in structures of varying thickness or unwanted residual material on the wafer surface. Thickness variations affect resistance, which can cause device failure or degraded performance. Residual interconnect material can create shorts between lines also leading to device failure and yield loss. A nondestructive method for directly measuring the thickness on submicron line-array structures is presented as a way to control Cu deposition and removal rates.
Device resistance is affected by the interconnect metal line thickness; therefore, process engineers need to control thickness to optimize yield. Typically, resistance values are not measured until electrical test, which provides functional evaluation but does not offer direct feedback on the performance of the copper deposition and removal processes. Changes in resistance may be due to thickness variations, but also to other types of process excursions. At the 65nm node and below, the challenges increase as new lower-k interlayer dielectric (ILD) materials exhibit different polishing behavior [1] and a significant portion of the interconnect structure includes features in the deep-submicron scale. Cross-sectional scanning electron microscopy (XSEM) can be used to measure interconnect thickness, but it is a slow and costly procedure because the wafer must be removed from the process and the test is destructive. This article presents data obtained using a nondestructive method for directly measuring the thickness on submicron line-array structures.
Post-CMP thickness variation
Final thickness is a direct function of the deposition and removal rates of the electroplating (EP) and chemical mechanical planarization (CMP) processes used to fabricate copper interconnects. The rate variations occur for a variety of reasons over a wide range of spatial and temporal scales. Deposition rates show wafer-scale changes are influenced by electrode placement and electrolyte distribution, while at the device scale, they are affected by linewidth and density [2].
Removal rates also vary over time and across a wide range of spatial scales. Over time, and from wafer-to-wafer, changes in slurry chemistry and pad wear will affect removal rates. At the wafer scale, CMP removal rates may vary in distinct, recognizable patterns that are related to the chemistry and mechanics of the CMP process. The removal rate also depends on the stage of the process and the material being polished. In the initial stages, when the entire surface is covered with bulk Cu, there is a long-range pattern dependency of ~6mm. After the bulk Cu is removed and regions of ILD are exposed, distinct differences in the polishing rate can be observed when the pattern density varies over a 50-200µm range. Finally, there are short-range dependencies that change the polishing rate of single lines over a 0.1-10µm range [3]. The plating process deposits a nonuniform layer that the CMP proceeds to remove at a nonuniform rate [4].
These nonuniformities result in two microscale phenomena - dishing and erosion - which are particularly troublesome. Dishing refers to greater removal rates in the center of larger planar structures such as copper test pads. Erosion refers to a similar phenomenon where the center of dense line arrays polishes more quickly than the edges. Both result from the fact that the CMP process must simultaneously polish three different types of material - the ILD, the barrier layer, and Cu - all of which have their own unique chemical and mechanical properties.
In general, ILD exhibits the lowest removal rates and Cu the greatest. A Cu pad surrounded by ILD, therefore, will be polished thinner in the middle than at the edges where it abuts the ILD. With erosion, variations in removal rates depend on both the linewidth and the line density (spacing) of the array. Dense line-array structures are common in semiconductor devices, and thickness variations within the array cause line-to-line resistance changes, degrading device performance.
The nonplanar surface that results from dishing and erosion can also affect photolithographic performance and create shorts between lines in overlying interconnect layers. The depressed topography of the overpolished region causes a loss of focus in photolithography, and can also be transferred to overlying layers of ILD and Cu. CMP on these upper layers then leaves areas of residual barrier material and/or Cu in the depressed region, failing to isolate individual lines.
As linewidths continue to shrink and new ILD materials are introduced, controlling post-CMP thickness variation is critical for high-yield manufacturing. Process-control measurements, whether made in test structures or on product die, must be able to measure a variety of structures, including submicron line arrays.
High-resolution profiling (HRP) is one technique commonly used to control Cu CMP processes. While HRP can provide excellent topography information that is useful in predicting subsequent photolithographic performance, it does not provide direct thickness measurement nor can it identify residual barrier or Cu. Thickness measurements can be derived, but only by making adjacent ellipsometric measurements of ILD thickness. Any variation in ILD thickness or variations in underlying topography from previous CMP operations will introduce errors into the HRP thickness measurements. Therefore, a single tool technique that directly measures Cu and ILD thickness is preferable.
A metrology solution
A metrology solution (MetaPULSE [Picosecond Ultrasonic Laser Sonar]) that uses a very short-duration laser pulse to briefly heat the sample surface, causing a rapid expansion and the launching of an acoustic wave that travels into the sample, addresses the problems discussed previously. When the wave encounters an interface between film layers, it is partially reflected back to the surface. The arrival of the echo at the surface causes a detectable change in reflectivity, and the elapsed time between echo induction and return, combined with knowledge of the acoustic properties of the sample material, permits a calculation of the distance between the surface and the underlying interface(s) [5, 6].
For planar structures larger than the 5×7µm spot formed by the laser, such as Cu bond pads, quantitative thickness measurements are relatively straightforward. In addition, material type can be automatically identified through qualitative changes in the amplitude and shape of the reflectance response (see Fig. 1). This is useful in detecting residual material after CMP, with the system automatically detecting the type of material - ILD, barrier layer, or Cu - and applying the appropriate signal processing to calculate its thickness. It also enables measurement of dishing profiles that track the thickness of the surrounding ILD and Cu across the structure.
When the features are small compared to the measurement spot size, such as submicron line areas, the measurement becomes more complicated. For example, on a 0.18µm line array with a 50% density, the spot covers almost 20 Cu lines and 20 ILD spacers. The reflectance signal from the Cu is therefore convolved with the signal from the ILD. For such applications, a position-sensitive detector (PSD) can be used to discriminate between the two signals. The PSD relies on the shift in the reflected laser beam when the sound wave reaches the surface and deflects it. These signals are much stronger for Cu than ILD and provide excellent signal-to-noise for Cu line arrays. The PSD detector can measure on both test sites and product die. A single measurement takes 2-5 sec, fast enough for in-line production monitoring. The accuracy and repeatability of the results are better than 1%.
Results
Thickness measurements were correlated with XSEM (Fig. 2). A recent study was performed on six different wafers that underwent different polishing processes. As would be expected, the Cu was thicker in the line arrays than on the pads on each wafer. The line-array structure tested consisted of 0.1μm 50% dense lines that will be used in a 65nm process. The correlation (R2) for both the line arrays and pads was better than 0.98 (Fig. 2).
 Figure 2. Correlation between XSEM and PULSE Cu thickness measurements on pads and on 0.1μm 50% dense line arrays. |
The XSEM correlation also showed that the measurements were accurate, both on pads and on dense line-array structures. The actual performance of the line arrays is determined by electrical testing results, and good correlation between the measurement method and electrical results are a requirement for acceptance of the technology. Figure 3 shows that thickness results for 10 wafers correlate with the inverse of line resistance (R2 = 0.9792).
 Figure 3. Correlation between PULSE thickness measurements and the inverse of line resistance as measured by electrical test. |
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Conclusion
Controlling Cu thickness in dual-damascene interconnect processes is critical to maintaining high yields, but conventional measurement techniques have deficiencies. XSEM provides high-quality measurements but is too slow for process control and too costly because it requires sacrificing the entire wafer. Electrical measurements are fast and relate directly to electrical functionality but are not performed in-line and do not offer specific information about the interconnect deposition and removal processes.
The PULSE method was shown to be capable of directly measuring thickness variations spanning the complete range of spatial scales, from full wafer to deep-submicron line arrays required for 65nm processes, on test structures, or on production die. Correlation with XSEM and electrical results was demonstrated and offers the immediate feedback and process-specific information required for effective process control.
Acknowledgments
This article is based on a paper that was originally presented at Semicon Korea, February 2, 2005 (S3: Dielectrics, Metals, New Materials and their Processes, “Production Monitoring of Copper CMP Process with Picosecond Ultrasonic Metrology,” by C. Kim, Rudolph Technologies). MetaPULSE-II and PULSE Technology are trademarks of Rudolph Technologies.
References
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- T. Park, et al., “Pattern Dependent Modeling of Electroplated Copper Profiles,” IITC, June 2001.
- T. Park, et al., “Overview of Methods for Characterization of Pattern Dependencies in Copper CMP,” Proc CMP-MIC, pp. 196-205, March 2000.
- D. Boning, et al., “Models for Pattern Dependencies: Capturing Effects in Oxide, STI, and Copper CMP,” Semicon West Technical Symposium: CMP Technology for ULSI Manufacturing, July 2001.
- C. Thomsen, et al., “Surface Generation and Detection of Phonons by Picosecond Light Pulses,” Phys. Rev. B, Vol. 34, pp. 4129-4138, 1986.
- C.J. Morath, et al., “Ultrasonic Multilayer Metal Film Metrology,” Solid State Technology, Vol. 40, No. 6, p. 85, June 1997.
Jana Clerico received her BS in electrical engineering from the Stevens Institute of Technology and her MBA from Fairleigh Dickinson U. She is manager of marketing communications, Rudolph Technologies Inc., One Rudolph Rd., Flanders, NJ 07836; ph 973/691-1300, [email protected].
Chris Morath received his PhD in condensed matter physics from Brown U. and his MBA from the Wharton School of Business Executive Program. He is director of marketing at Rudolph Technologies.