Stacking chip-scale packages
06/01/2005
The practice of stacking packaged DRAMs to achieve higher-density memories has been around for decades. In fact, DRAM stacking dates back to IBM Corp.’s PC AT model in the mid-1980s when dual in-line packages were combined to achieve 512Kbytes of system memory. The adoption of thin small-outline packages (TSOP) in the early 1990s moved memory stacking into the mainstream, but now the DRAM industry is transitioning to chip-scale packages (CSP). These new packages are lightweight and have better electrical and thermal properties than TSOPs while offering near die-size packaging. Of the many features CSPs have to offer, however, facilitating chip stacking is not one of them.
CSPs are defined as a single-chip package that is no more than 1.2× the size of the die. For DRAMs, that means the packages will range from the size of the ball array to 12.3×22mm, which is the largest package that will fit on dual in-line memory modules (DIMM) using conventional techniques. Stacking 64-pin TSOPs has been simpler because these packages are always the same size and shape, but the new CSPs for DRAMs vary in three dimensions. CSPs also vary in “ballout” (the footprint of the ball grid array), and they must support memory speeds approaching 1Gbit/sec. CSP stacking has become a moving target, and managing the higher thermal output presents unique challenges.
However, CSP stacking can be made as straightforward as TSOP stacking. A flex-circuit interconnect system, called High Performance Stakpak, has been developed for CSP stacking, utilizing standard surface-mount technology and innovative design concepts to address signal integrity, heat dissipation, and coefficient of thermal expansion (CTE) in a stack.
Stacking is more than placing chips on top of each other and connecting the signals. First and foremost is the need to protect signal integrity. With the next double-data rate (DDR) DRAMs offering speed grades of 533, 667, and 800MHz, getting a clean signal and meeting the timing requirements are not guaranteed in a stack. Along with higher speeds comes higher power. The power to drive higher speeds scales by the square of the frequency (P = cvF2). The stacking technology will have to minimize the temperature rise of the DRAM stack, yet the increase in stack size has to be minimal. The stack must fit on the DIMM, which must fit in the slots on the computer’s motherboard. The stacking solution also has to be “vendor-neutral” so that users do not have to qualify multiple stacking technologies. Finally, the stacking solution must be reliable.
Stacking alternatives
There are several different methods to stack DRAMs. Package stacking uses commodity-packaged devices combined with an interconnect system that ties the devices together. Die stacking is performed inside a single package that accommodates two die. A third emerging option employs a stacking package that puts die in a nonstandard, intermediate package for testing and then stacking.
Die stacking has an advantage when there are stringent requirements on the height of memory components, such as in portable and handheld systems. Die stacking also is best suited when there is a fixed quantity of products and predictable production schedules because of longer lead times required to assemble multidie memories. There are additional costs due to yield issues or expenses of using known good die (KGD) in multidie packages.
Stacking with nonstandard packages addresses the yield issues of multidie packages. A thin intermediate package holds the die during burn-in and testing, before stacking. This assembly comes close to the height of dual-die packages, but they still present lead-time and inventory issues. These types of packages are also not used by all DRAM manufacturers.
The stacking of DRAMs in standard packages solves the difficulty of forecasting demand. Packaged DRAMs can be tested as fully functional using standard automatic test equipment prior to the stacking process. But the advent of CSPs for DDR DRAMs has complicated this widely used stacking practice for PC and workstation memory applications.
 Figure 1. The building blocks of Staktek’s CSP-stacking interconnect system. |
To address the challenges of CSP stacking, Staktek has created an interconnect system that incorporates a polyimide-based flex circuit folded around an aluminum mandrel (Fig. 1). The flex circuit interconnect system has a minimum width penalty of 1mm and does not exceed JEDEC’s maximum spec of 12.5mm. When placed on a DIMM, the maximum height of the stacks does not exceed the JEDEC’s DIMM limit of 6.75mm.
The CSP-stacking system also addresses signal integrity issues by matching the length of interconnect lines to eliminate skew. The impedance of the interconnect matches the module to eliminate reflections. Thermal issues are addressed by the mandrel, which acts as a heat spreader to provide thermal coupling between the devices in the stack. Although counterintuitive, the device with the greater rise in temperature is not the bottom device in the stack but rather the top one, which is exposed to airflow (Fig. 2). With the interconnect system, stacks provide a greater thermal mass, which dissipates heat better than a monolithic DRAM package.
 Figure 2. Spectrum from thermal tests shows the hottest temperatures (orange and yellow) at the top of the DDR memory stack. |
Unlike TSOPs, CSPs have interconnect balls on the package bottom. Consequently, the interconnect path must go around the edges of the CSP. This introduces a width penalty, but the design of the mandrel and flex circuit in the Stakpak minimizes this width. The mandrel also makes this stacking approach a universal solution for any CSP-housed DRAM.
Chip-scale packaging presents manufacturing and reliability issues due to the potential for CTE mismatch, which can create stress on the array of balls and interconnects. This can lead to balls cracking and connections failing. The Stakpak effectively doubles the length of the ball, thereby reducing the stress. CSPs also can suffer from coplanarity issues and are somewhat fragile. Inserting the devices in a mandrel helps to make the CSP rigid and protects the parts from cracking by keeping them flat. If a device in a stack fails, for whatever reason, the construction can be disassembled and good devices recovered for reuse.
In this stacking process, standard surface-mount techniques are used. The CSP packages are first inserted into the mandrel to standardize the width of devices as well as dissipate heat from the stack. The device is connected to the flex circuit, which is wrapped around the mandrel. Pads on the flex circuit provide a landing pattern for the second device. Connections are reflowed, and the final operation is to place an array of balls on the bottom flex circuit for connection to the DIMM.
What’s next
Stacking was originally used to achieve higher memory densities than what was available in single-chip DRAM devices for modules. Looking ahead to higher-speed DDR2 and DDR3 devices, faster clock rates will limit the number of DIMMs that will work on a memory channel. As the number of DIMM slots decreases, DRAM stacking will be required to maintain system memory sizes. The die sizes of next-generation 2Gbit DRAMs are currently projected to be too big for current standard DIMMs. To build a single-density DIMM, devices may have to be stacked.
Stacking CSPs can become a viable solution to achieve higher memory capacities in industry-standard form factors, but new interconnect design concepts are needed. The stacking overhead must be kept to a minimum so module sizes comply with JEDEC standards for system manufacturers. A mandrel-based design can result in a DRAM vendor-neutral, high-volume stacking process with improved thermal and electrical properties. The addition of the flex circuit and a second array of solder balls between the device and the module significantly increases the reliability of the connections.
Acknowledgment
High Performance Stakpak is a registered trademark of Staktek Holdings Inc.
Paul Goodwin is director of technical marketing at Staktek Holdings Inc., 8900 Shoal Creek Blvd., Suite 125, Austin, TX 78757; ph 512/454-9531, fax 512/454-9409, e-mail [email protected].